Abstract: A high rotor pole switched reluctance machine (HRSRM) employs an axial and radial mirroring concept and is represented by a first Multiple Rotor Pole (MRP) formula and second Multiple Stator Pole (MSP) formula. A multiple rotor HRSRM comprises at least two rotors each having a plurality of rotor poles and at least one stator having a plurality of stator poles. The at least two rotors and the at least one stator are positioned about a central axis with the stator placed between, and laterally adjacent to the rotors. A multiple stator HRSRM comprises at least two stators having a plurality of stator poles and at least one rotor having a plurality of rotor poles. The at least two stators and at least one rotor are positioned about a central axis with the rotor placed between and laterally adjacent to the stators.

Abstract: Examples described herein include improved systems and methods for performing erasures and edits within a graphical user interface. A computing device can include a processor that detects skin contact with a touch-screen display of the computing device. The processor can also detect, based on the skin contact, a gesture that indicates an erasure function. Based on that determination, the processor executes the erasure function.

Abstract: A high rotor pole switched reluctance machine (HRSRM) employs an axial and radial mirroring concept and is represented by a first Multiple Rotor Pole (MRP) formula and second Multiple Stator Pole (MSP) formula. A multiple rotor HRSRM comprises at least two rotors each having a plurality of rotor poles and at least one stator having a plurality of stator poles. The at least two rotors and the at least one stator are positioned about a central axis with the stator placed between, and laterally adjacent to the rotors. A multiple stator HRSRM comprises at least two stators having a plurality of stator poles and at least one rotor having a plurality of rotor poles. The at least two stators and at least one rotor are positioned about a central axis with the rotor placed between and laterally adjacent to the stators.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

Abstract: A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

Abstract: Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

Abstract: A digital controller is easily implemented for variable speed or torque control of an electric motor or generator by using a comparator to determine a choice of control state outputs.

Abstract: Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

Abstract: A switched reluctance machine (SRM) having a rotor and stator pole numerical relationship of S number of stator poles and R number of rotor poles, where R=2S?2, when S is greater than 4; provides improved power density, torque production, torque ripple, and acoustic noise, and is readily adaptable to existing hardware such as known controllers and the like.

Abstract: A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: Internal bus observation techniques for an electronic module or integrated circuit. In one embodiment, a disclosed apparatus includes observation logic to observe an observed bus and a debug buffer. The observation logic captures a record reflecting signal observed on the observed bus. The debug buffer is coupled to the observation logic to receive the record that reflects signal observed by the observation logic. The debug buffer generates a transaction to transfer the record to a storage device to store the record.

Abstract: A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.