Patents by Inventor Piyush Patel

Piyush Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190358253
    Abstract: A pharmaceutical composition of Capecitabine, wherein the composition includes immediate release Capecitabine and extended release Capecitabine. Further disclosed is a process for the preparation of the composition.
    Type: Application
    Filed: February 5, 2018
    Publication date: November 28, 2019
    Applicant: INTAS PHARMACEUTICALS LTD.
    Inventors: Kashyap GANDHI, Piyush PATEL, Manish PATEL, Manish CHAUHAN, Ashish SEHGAL
  • Publication number: 20190332550
    Abstract: A memory management unit (MMU) is disclosed. The MMU is configured to receive a translation request from a processing system, wherein the translation request specifies a virtual address to be translated, search a page table stored in a physical memory system for a page table entry that specifies the virtual address, receive a translation lookaside buffer invalidation (TLBI) signal from the processing system, wherein the TLBI signal specifies the virtual address, in response to receiving the TLBI signal specifying the virtual address, invalidate a translation lookaside buffer (TLB) entry in a TLB, wherein the invalidated TLB entry specifies the virtual address and restart the search of the page table for the page table entry that specifies the virtual address.
    Type: Application
    Filed: April 26, 2018
    Publication date: October 31, 2019
    Inventors: Jason NORMAN, Piyush PATEL, Rakesh ANIGUNDI, Sadayan Ghows Ghani SADAYAN EBRAMSAH MO ABDUL
  • Publication number: 20190241543
    Abstract: Deuterated domperidone compositions, methods of synthesis, methods of use, and dosing formulations providing beneficial safety and other effects.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Catherine Pearce, Jon Isaacsohn, Piyush Patel
  • Publication number: 20190201417
    Abstract: A formulation of a topical steroid for therapy of a mucosa or dermatological lesion, such as but not limited to a lichen planus lesion or an aphthous ulcer.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 4, 2019
    Inventors: Drore EISEN, Piyush PATEL, Catherine PEARCE, Jon ISAACSOHN
  • Patent number: 10310882
    Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Zeng, Azzedine Touzni, Philip Mueller, Jr., Piyush Patel
  • Patent number: 10266516
    Abstract: Deuterated domperidone compositions, methods of synthesis, methods of use, and dosing formulations providing beneficial safety and other effects.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 23, 2019
    Assignee: CINRX PHARMA, LLC
    Inventors: Catherine Pearce, Jon Isaacsohn, Piyush Patel
  • Publication number: 20190087351
    Abstract: According to various aspects, a memory management unit (MMU) having multiple parallel translation machines may collect transactions in an incoming transaction stream and select appropriate transactions to dispatch to the parallel translation machines. For example, the MMU may include a dispatcher that can identify different transactions that belong to the same address set (e.g., have the same address translation) and dispatch one transaction from each transaction set to an individual translation machine. As such, the dispatcher may be used to ensure that multiple parallel translation machines do not perform identical memory translations, as other transactions that share the same address translation may obtain the translation results from a translation lookaside buffer.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 21, 2019
    Inventors: Sadayan Ghows Ghani Sadayan Ebramsah Mo ABDUL, Piyush PATEL, Michael TROMBLEY, Rakesh ANIGUNDI, Jason NORMAN, Aaron SEYFRIED
  • Patent number: 10114756
    Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius, Lucian Codrescu
  • Patent number: 10089275
    Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Publication number: 20170298046
    Abstract: Deuterated domperidone compositions, methods of synthesis, methods of use, and dosing formulations providing beneficial safety and other effects.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Inventors: Catherine SOLDANO, Jon ISAACSOHN, Piyush PATEL
  • Patent number: 9606818
    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
  • Publication number: 20160371221
    Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 22, 2016
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Publication number: 20160371208
    Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 22, 2016
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Patent number: 9478599
    Abstract: An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and ceramics, includes a base and a cap sealed to the base. The metal inductor includes a metal layer patterned on at least one of the cap and base of the package. The base may also include first and second electrically conductive vias therein, which are electrically connected to first and second terminals of the inductor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 25, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel
  • Publication number: 20160283262
    Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Inventors: Thomas Zeng, Azzedine Touzni, Philip Mueller, JR., Piyush Patel
  • Patent number: 9445536
    Abstract: A crystal oscillator fabrication method includes depositing mounting cement onto first and second mounting pads on a substrate to thereby define first and second electrode adhesion bumps. First and second electrodes of a crystal oscillator are electrically connected to the first and second mounting pads by contacting the first and second electrodes to the first and second electrode adhesion bumps and then curing the adhesion bumps. Next, mounting cement is deposited onto the first electrode and onto a portion of the first electrode adhesion bump to thereby define a top electrode adhesion extension. The top electrode adhesion extension is then cured.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 13, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel
  • Patent number: 9393307
    Abstract: The present invention relates to a composition comprising caspofungin or a pharmaceutical acceptable salt thereof and succinate or lactate as a buffering agent.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: July 19, 2016
    Assignee: XELLIA PHARMACEUTICALS APS
    Inventors: Swapnil P. Shirode, Piyush Patel, Suresh Gidwani, Neil Parikh, Atul Patil, Anita Bevetek Mochnik
  • Patent number: 9396011
    Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Thomas M. Zeng, Azzedine Touzni, Philip T. Mueller, Jr., Piyush Patel
  • Patent number: 9397151
    Abstract: A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the integrated circuit substrate. The inductor may include a plurality of arcuate-shaped segments and may be patterned to be symmetric about a center-tapped portion thereof. The cap may also include a magnetic material therein that increases an effective inductance of the inductor relative to an otherwise equivalent cap and inductor combination that is devoid of the magnetic material.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 19, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Kenneth L. Astrof, Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel, Jitesh Shah
  • Patent number: 9306537
    Abstract: An integrated circuit device includes an integrated circuit substrate having a two piece package thereon. The package has a hermetically sealed cavity therein and a crystal resonator within the cavity. The crystal resonator includes at least one electrode electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package may include a material selected from a group consisting of glass and ceramics. The crystal resonator includes a crystal blank and first and second electrodes on first and second opposing sides of the crystal blank. The package includes a base having a recess therein and a cap hermetically sealed to the base. The cap includes first and second electrical traces thereon, which are electrically connected to the first and second electrodes of the crystal resonator.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 5, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Robert A. Gubser, Ajay Kumar Ghai, Viresh Piyush Patel