Abstract: Methods and systems are provided for performing combinational loop emulation. The methods and systems access a circuit design comprising a loop break element in a combinational loop path, where the loop break element comprises an input and an output. The methods and systems detect a change between the input of the loop break element and the output of the loop break element. The methods and systems identify a type of consumer of the output of the loop break element in the combinational loop path. The methods and systems determine whether to apply an extra clock cycle to the loop break element based on the type of consumer of the output of the loop break element and the detected change between the input and the output of the loop break element.

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes a method of hardware emulation on a computer. The method may include reading in, by the computer, a hardware description language file and a low power intent file and compiling the hardware description language file and the low power intent file into an emulation image. Embodiments may include loading, the emulation image into an emulator, running, the emulation image under a test environment including using a coverage counter specific to low power coverage, created based on the hardware description language file and the low power intent file, using the coverage counters to inform the test environment, generating, by the computer, a report file including a set of low power coverage metrics based on a low power coverage data item, and presenting the report file to a user via a user interface.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.

Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.