Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.

Abstract: A force sensing method, applied to a force sensing system comprising a plurality of force sensors and a touch sensing surface, comprising: (a) determining a first location of a first object on the touch sensing surface; (b) defining a first force sensing region according to the first location; and (c) computing a first system sensing force which the first object causes to the touch sensing surface according to the first location, and according to at least one sensor sensing force of a first part of the force sensors corresponding to the first force sensing region. The present invention also discloses a force sensing system which uses the above-mentioned force sensing method, and an efficient force sensor calibration method. Noises can be reduced and power consumption can be decreased, since only sensor sensing forces of force sensors near the object are used for computing the system sensing force.

Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: A fabric of a cup body of a brassiere includes an inner textile layer, an outer textile layer and a middle textile layer. A first weaving region and a second weaving region of the outer textile layer respectively include a plurality of composite yarns. Each of the composite yarns includes a first yarn and a second yarn. A melting point of the first yarn is lower than a melting point of the second yarn, and an offset rate of the second yarn relative to the first yarn is from 5% to 300%. A content of the composite yarns in the first weaving region is greater than that in the second weaving region. A content of the composite yarns in a third weaving region of the outer textile layer is less than that in the second weaving region. The first weaving region is at a lifting area of the cup body.

Abstract: An extremely high throughput (EHT) station (STA) configured for trigger based (TB) transmission may decode an trigger frame (TF) received from an access point (AP). The TF may include an assignment of resources comprising one or more 20 MHz channels. The EHT STA may determine which of the one or more assigned channels are available for transmission and which of the allocated channels are unavailable when the EHT STA is assigned more than one 20 MHz channel. The EHT STA may encode a EHT TB PPDU in response to the trigger frame. The EHT TB PPDU may be encoded to include an EHT preamble followed by a data field. The EHT preamble may be encoded to indicate channel availability. The EHT STA may generate signalling to cause the EHT STA to transmit the encoded EHT TB PPDU only on the assigned channels that have been determined to be available.

Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Abstract: A modulating device is provided. The modulating device includes multiple modulating elements, multiple pixel circuits, and a compensation circuit. The pixel circuits are electrically connected to the modulating elements correspondingly. The compensation circuit includes a driving unit, a voltage source, and a current source. The driving unit provides a driving signal to the pixel circuits. The voltage source is electrically connected to the driving unit. The voltage source provides a constant voltage to the pixel circuits. The current source is electrically connected to the driving unit. The current source provides a constant current to the pixel circuits.

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

Abstract: The present disclosure provides a method for preparing mesenchymal stem cell-derived extracellular vesicle, the mesenchymal stem cell-derived extracellular vesicle prepared by the method, and use of the mesenchymal stem cell-derived extracellular vesicle for reducing adipogenesis and treating osteoarthritis. The mesenchymal stem cell-derived extracellular vesicle of the present disclosure achieves the effect of reducing adipogenesis and treating osteoarthritis through various efficacy experiments.

Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.

Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

Abstract: The invention provides a method for improving sarcopenia of a subject in need thereof by using Phellinus linteus, in which the method includes administering an effective dose of composition to the subject, and the composition includes Phellinus linteus (NITE BP-03321 and BCRC 930210) as an effective substance. By using the aforementioned composition including an extract of a fermented product of the Phellinus linteus and/or its derivative, diameters of myotubes, amounts of muscles and muscle muscular endurance can be maintained, thereby improving sarcopenia.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: A modular assembly for opto-electronic systems has a substrate on which various photonic integrated circuit (PIC) chips and electronic integrated circuit (EIC) chips are mounted. One or more waveguide (WG) chips mounted on the substrate align the optical communication between the PIC chips and fiber blocks for optical fibers. Preconfigured electrical connections in the substrate allow the PIC and EIC chips to communicate with one another and to communicate with solder bumps on the substrate for integration of the modular assembly with other electronic components.