Abstract: The present invention provides a magnetic power machine comprising a path portion, a rotor portion and a stator portion, wherein a rolling path is provided around the path portion; the rotor portion is provided around and outside the path portion and capable of rotating, and has an output shaft on one end that outputs power; a plurality of movable rods are provided on the rotor portion; a force-receiving arm and a roller are respectively provided on a top and a bottom of each of the movable rods; the roller moves along the rolling path; the force-receiving arm unfolds or folds as the roller moves up or down on the rolling path; the stator portion is provided around and outside the rotor portion; a plurality of force-exerting arms are provided opposite to the force-receiving arms on an inner edge of the stator portion; a magnetic force-exerting unit of single-sheet N-S arrangement and a magnetic force-receiving unit of triple-sheet N-S arrangement are respectively provided on the force-exerting arm and the for

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: A method for performing access management of a memory device in a predetermined communications architecture with aid of automatic parameter setting and associated apparatus are provided. The method includes: utilizing the memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one adaptive flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch. The adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.

Abstract: A decoder includes a demultiplexer and a number (P) of ADCs, where P?2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M?2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.

Abstract: A funnel storage device is provided, wherein the funnel storage device includes: a tubular member including a first end portion and a second end portion; a receiving member connected to the first end portion, in communication with an interior of the tubular member, and tapering in a direction toward the first end portion; and a base connected to the second end portion, not in communication with the interior of the tubular member, and expanding in a direction away from the second end portion.

Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.

Abstract: Provided herein are antibodies or antigen binding fragments thereof having a binding specificity for p95HER2 or for CD73, bispecific antibodies comprising a first antigen binding region that binds to p95HER2 or CD73 and a second antigen binding region that binds to an immune checkpoint molecule or an immune stimulatory molecule, and antibody-drug conjugates thereof. Also provided herein are pharmaceutical compositions comprising the antibodies, antigen binding fragments thereof, bispecific antibodies or antibody drug conjugates thereof, and methods of use thereof. The methods of use include method of treating cancer.

Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: A receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator performs channel compensation on an input data signal to generates a feed-in data signal. The decoder demultiplexes a to-be-decoded data signal that originates from the feed-in data signal into multiple demultiplexed data signals, and decoding the demultiplexed data signals respectively into multiple decoded signals. Based on a decoded output that originates from the decoded signals, the adaptive controller performs adaptive calibration on the channel compensator to adjust a gain of the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals that is generated before the generation of the first sample of the decoded signals.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: The subject system may be implemented by at least one processor configured to, by a system process, receive a request for one or more content item bundles, obtain the one or more content item bundles for presentation of the one or more content item bundles, receive a selection of a content item bundle from the presented one or more content item bundles, and providing, to the application process, one or more content items of the selected content item bundle. The one or more content item bundles are inaccessible to an application process before they are provided to the application process by the system process.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.

Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.

Abstract: An IC device includes a first power terminal, an IO pad, a first ESD protection device coupled between the first power terminal and IO pad, a first trigger current source device coupled between the first power terminal and the IO pad, and a substrate over which the first ESD protection device and first trigger current source device are formed. The first ESD protection device includes a parasitic BJT having a collector and an emitter coupled between the IO pad and first power terminal, and a base coupled via a substrate resistance to a well tap coupled to the first power terminal. The first trigger current source device, in response to an ESD voltage on the IO pad, becomes conductive and causes discharge of the ESD voltage through the first ESD protection device to the first power terminal.

Abstract: A decoder includes a demultiplexer and a number (P) of ADCs, where P?2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M?2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.

Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.