Abstract: Machine learning is a process that learns a model from a given dataset, where the model can then be used to make a prediction about new data. In order to reduce the size, computation, and latency of a machine learning model, a compression technique can be employed which includes model sparsification and quantization. To limit the extent to which the quality of the model is impacted when uniformly applying sparsification and quantization to all values of the model, the present disclosure provides for a hybrid sparsification and quantization of the model.

Abstract: Systems and methods for efficient convolution based on matrix multiply and add (MMA) are described. An example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of MMA instructions and shift instructions while reusing activation elements already loaded to the datapath or associated memory over a plurality of MMA operations. Associated methods are also described.

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: Apparatuses, systems, and techniques to determine a configuration based at least in part on data stored by at least one data structure of a workload at runtime, and transform the workload into a sparse workload based at least in part on the configuration. In at least one embodiment, one or more sparse workloads (e.g., one or more sparse neural networks) are generated based at least in part on, for example, one or more workloads (e.g., one or more neural networks).

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.

Abstract: Hierarchical structured sparse parameter pruning and processing improves runtime performance and energy efficiency of neural networks. In contrast with conventional (non-structured) pruning which allows for any distribution of the non-zero values within a matrix that achieves the desired sparsity degree (e.g., 50%) and is consequently difficult to accelerate, structured hierarchical sparsity requires each multi-element unit at the coarsest granularity of the hierarchy to be pruned to the desired sparsity degree. The global desired sparsity degree is a function of the per-level sparsity degrees. Distribution of non-zero values within each multi-element unit is constrained according to the per-level sparsity degree at the particular level of the hierarchy. Each level of the hierarchy may be associated with a hardware (e.g., logic or circuit) structure that can be enabled or disabled according to the per-level sparsity.

Abstract: Accelerators are generally utilized to provide high performance and energy efficiency for tensor algorithms. Currently, an accelerator will be specifically designed around the fundamental properties of the tensor algorithm and shape it supports, and thus will exhibit sub-optimal performance when used for other tensor algorithms and shapes. The present disclosure provides a flexible accelerator for tensor workloads. The flexible accelerator can be a flexible tensor accelerator or a FPGA having a dynamically configurable inter-PE network supporting different tensor shapes and different tensor algorithms including at least a GEMM algorithm, a 2D CNN algorithm, and a 3D CNN algorithm, and/or having a flexible DPU in which a dot product length of its dot product sub-units is configurable based on a target compute throughput that is less than or equal to a maximum throughput of the flexible DPU.

Abstract: Accelerators are generally utilized to provide high performance and energy efficiency for tensor algorithms. Currently, an accelerator will be specifically designed around the fundamental properties of the tensor algorithm and shape it supports, and thus will exhibit sub-optimal performance when used for other tensor algorithms and shapes. The present disclosure provides a flexible accelerator for tensor workloads. The flexible accelerator can be a flexible tensor accelerator or a FPGA having a dynamically configurable inter-PE network supporting different tensor shapes and different tensor algorithms including at least a GEMM algorithm, a 2D CNN algorithm, and a 3D CNN algorithm, and/or having a flexible DPU in which a dot product length of its dot product sub-units is configurable based on a target compute throughput.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: A fabricating method of a shielded gate MOSFET is provided, includes the steps of forming a semiconductor substrate having a trench, forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench, forming a source polycrystalline silicon region in the trench, forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer, depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region, forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench, forming a gate polycrystalline silicon region in the trench, and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A fabricating method of a shielded gate MOSFET is provided, including steps of: forming a semiconductor substrate having a trench; forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench; forming a source polycrystalline silicon region in the trench; forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer; depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region; forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench; forming a gate polycrystalline silicon region in the trench; and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A projecting device is provided. The projecting device is adapted to assembling with an electronic device. The projecting device comprises a main body, a light emitting portion, a rotating portion, and an adjusting portion. The main body includes a first opening and a second opening. The light emitting portion is disposed in the main body, and transmits a light through the first opening. The rotating portion is disposed in the main body and connected with the light emitting portion. The adjusting portion is disposed in the second opening and connected with the rotating portion. The light emitting portion drives the rotating portion to rotate through the adjusting portion to adjust the angle of the light.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: A projecting device is provided. The projecting device is adapted to assembling with an electronic device. The projecting device comprises a main body, a light emitting portion, a rotating portion, and an adjusting portion. The main body includes a first opening and a second opening. The light emitting portion is disposed in the main body, and transmits a light through the first opening. The rotating portion is disposed in the main body and connected with the light emitting portion. The adjusting portion is disposed in the second opening and connected with the rotating portion. The light emitting portion drives the rotating portion to rotate through the adjusting portion to adjust the angle of the light.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: A low-cost waist adhering material for paper diaper for mass production and easy application comprises a replacement material. The replacement material is composed of a non-textile fabric layer disposed at a top end for connecting with hooks of a paper diaper, and a molded positioning layer disposed underneath the non-textile fabric layer and on a surface of the paper diaper for positioning the non-textile fabric layer. The non-textile fabric layer has at least one through hole area. The through hole area is composed of a plurality of through holes spaced at intervals penetrating through the non-textile fabric layer.

Abstract: A leakage proof base material for paper diaper is provided which is more convenient to use, suitable to be mass produced, more skin-friendly and with a lower cost. The leakage proof base material for paper diaper comprises a leakage proof base material which is composed of a leakage proof membrane as a top layer and a non-textile fabric layer as a bottom layer, and surfaces of the leakage proof membrane and the non-textile fabric layer are combined together partially or entirely. At least one through hole area is disposed on the non-textile fabric layer, the through hole area is composed of a plurality of through holes which are penetrated through the non-textile fabric layer and are spaced at intervals.

Abstract: A diaper having an improved conjugated structure that is convenient, low-cost and easy for mass production is disclosed. The diaper includes a side wing having a magic hook located thereon and a rear thin sheet having an anti-leaking layer and a non-textile fabrics layer conjugated entirely or partially. The conjugation strength between the magic hook and the rear thin sheet is about 100 to 700 g/inch at 180 degrees, and the shear stress at 180 degrees is over 1000 g/inch. With the conjugation between the magic hook and the rear thin sheet, the user can randomly attach the magic hook to the surface of the non-textile fabrics layer to adjust the tightness of the diaper.