Patents by Inventor Po-Chang Lin
Po-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250247664Abstract: An audio time latency-based spatial orientation method is disclosed. A VR device is paired and connected with a plurality of speakers. Multiple audio time latencies from the VR device to the speakers are calculated. Current positions of the speakers relative to the VR device are calculated based on the audio time latencies and a virtual boundary is defined. Threshold values of the speakers relative to the virtual boundary are defined. It is determined whether the VR device is close to or beyond the virtual boundary according to the threshold values. If the VR device is close to or beyond the virtual boundary, the VR device issues an alarm.Type: ApplicationFiled: January 30, 2024Publication date: July 31, 2025Inventor: PO-CHANG LIN
-
Patent number: 12284503Abstract: An audio latency calibration method is disclosed. A master speaker and a slave speaker are located at a separation distance from each other, and a paring process is performed. As the paring process is completed, multiple latency time period parameters are obtained relating to the master and slave speakers. The latency time period parameters comprise: T1+T2 representing the time that the master speaker sends an audio signal to the slave speaker, T3+T4 representing the time that the audio signal is transmitted from the slave speaker to a microphone of the master speaker, T5 representing the time that a trumpet of the master speaker plays the audio signal and T3? representing the time that a microphone of the master speaker receives the audio signal. Thus, the way to synchronously play audio signals can be achieved.Type: GrantFiled: January 5, 2023Date of Patent: April 22, 2025Assignee: AMBIT MICROSYSTEMS (SHANGHAI) LTD.Inventor: Po-Chang Lin
-
Publication number: 20250098238Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.Type: ApplicationFiled: October 23, 2023Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Tien-Shan Hsu, Po-Chang Lin, Lung-En Kuo, Hao-Che Feng, Ping-Wei Huang
-
Publication number: 20240420991Abstract: A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.Type: ApplicationFiled: July 7, 2023Publication date: December 19, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jing-Wen Huang, Chih-Yuan Wen, Lung-En Kuo, Po-Chang Lin, Kun-Yuan Liao, Chung-Yi Chiu
-
Publication number: 20240379670Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.Type: ApplicationFiled: June 6, 2023Publication date: November 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
-
Publication number: 20240236572Abstract: An audio latency calibration method is disclosed. A master speaker and a slave speaker are located at a separation distance from each other, and a paring process is performed. As the paring process is completed, multiple latency time period parameters are obtained relating to the master and slave speakers. The latency time period parameters comprise: T1+T2 representing the time that the master speaker sends an audio signal to the slave speaker, T3+T4 representing the time that the audio signal is transmitted from the slave speaker to a microphone of the master speaker, T5 representing the time that a trumpet of the master speaker plays the audio signal and T3? representing the time that a microphone of the master speaker receives the audio signal. Thus, the way to synchronously play audio signals can be achieved.Type: ApplicationFiled: January 5, 2023Publication date: July 11, 2024Inventor: PO-CHANG LIN
-
Patent number: 11855007Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.Type: GrantFiled: April 27, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
-
Publication number: 20230335622Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
-
Publication number: 20230330901Abstract: Present invention is related to an evenly heating method for enhancing heating result having steps of: introducing a foam material into a mould, compressing the foam material by a mechanical force to a preset thickness or status, and heating the foam material to obtain a foam product. By applying the mechanical force to the foam material during the process, the foam material could be compressed into a more compact status in order to be heated more evenly and thoroughly. The present invention provides the foam product in good quality by a simple and low cost heating method.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventor: Po-Chang Lin
-
Patent number: 11731323Abstract: Present invention is related to a microwave and electromagnetic heated foaming method, mold and foaming material thereof. The microwave and electromagnetic heated foaming method comprises steps of adding a foam material into a mold, simultaneously applying a microwave and electromagnetic energy toward the mold under a normal or low pressure, and the microwave and electromagnetic energy made the foam material into molded foam body. The mold of the present invention has a microwave penetrating part and an electromagnetic heating part. The microwave penetrating part has an extruded bottom that is corresponded to a dented top of the electromagnetic heat penetrating part. By utilizing the microwave and electromagnetic energy, the present invention is about to provide an efficient way for processing the foaming material compared to the conventional infrared or electrical heated tube heating and achieve the foam method that can be executed under normal or low pressure.Type: GrantFiled: April 15, 2020Date of Patent: August 22, 2023Assignee: Herlin Up Co., Ltd.Inventors: Po-Chang Lin, Kuang-Tse Chin, Jung-Hsiang Hsieh, Ya-Chun Yu
-
Patent number: 11735646Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: GrantFiled: November 6, 2020Date of Patent: August 22, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
-
Patent number: 11515213Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.Type: GrantFiled: January 7, 2021Date of Patent: November 29, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chung Chen, Po-Chang Lin, Huang-Ren Wei, Wei-Lun Chou
-
Publication number: 20220254737Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
-
Publication number: 20220208612Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.Type: ApplicationFiled: January 7, 2021Publication date: June 30, 2022Inventors: Chih-Chung Chen, Po-Chang Lin, Huang-Ren Wei, Wei-Lun Chou
-
Patent number: 11348879Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.Type: GrantFiled: September 24, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
-
Patent number: 10965264Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.Type: GrantFiled: May 3, 2019Date of Patent: March 30, 2021Assignee: Rafael Microelectronics, Inc.Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng
-
Publication number: 20210057551Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
-
Publication number: 20210013159Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
-
Patent number: 10868148Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: GrantFiled: December 4, 2018Date of Patent: December 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
-
Publication number: 20200350881Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.Type: ApplicationFiled: May 3, 2019Publication date: November 5, 2020Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng