Patents by Inventor Po-Chang Lin
Po-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929767Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.Type: GrantFiled: August 16, 2022Date of Patent: March 12, 2024Assignee: MEDIATEK INC.Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
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Publication number: 20240076417Abstract: The present disclosure provides a method for manufacturing an auto-crosslinked hyaluronic acid gel, comprising conducting auto-crosslinking reaction of a colloid containing hyaluronic acid continuously at low temperature in an acidic environment, and treating the reaction product with steam at high temperature to obtain the auto-crosslinked hyaluronic acid gel with high viscosity.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Applicant: SCIVISION BIOTECH INC.Inventors: TAI-SHIEN HAN, TSUNG-WEI PAN, TOR-CHERN CHEN, CHUN-CHANG CHEN, PO-HSUAN LIN, LI-SU CHEN
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Patent number: 11923433Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.Type: GrantFiled: March 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
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Patent number: 11855007Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.Type: GrantFiled: April 27, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Publication number: 20230330901Abstract: Present invention is related to an evenly heating method for enhancing heating result having steps of: introducing a foam material into a mould, compressing the foam material by a mechanical force to a preset thickness or status, and heating the foam material to obtain a foam product. By applying the mechanical force to the foam material during the process, the foam material could be compressed into a more compact status in order to be heated more evenly and thoroughly. The present invention provides the foam product in good quality by a simple and low cost heating method.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventor: Po-Chang Lin
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Publication number: 20230335622Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Patent number: 11731323Abstract: Present invention is related to a microwave and electromagnetic heated foaming method, mold and foaming material thereof. The microwave and electromagnetic heated foaming method comprises steps of adding a foam material into a mold, simultaneously applying a microwave and electromagnetic energy toward the mold under a normal or low pressure, and the microwave and electromagnetic energy made the foam material into molded foam body. The mold of the present invention has a microwave penetrating part and an electromagnetic heating part. The microwave penetrating part has an extruded bottom that is corresponded to a dented top of the electromagnetic heat penetrating part. By utilizing the microwave and electromagnetic energy, the present invention is about to provide an efficient way for processing the foaming material compared to the conventional infrared or electrical heated tube heating and achieve the foam method that can be executed under normal or low pressure.Type: GrantFiled: April 15, 2020Date of Patent: August 22, 2023Assignee: Herlin Up Co., Ltd.Inventors: Po-Chang Lin, Kuang-Tse Chin, Jung-Hsiang Hsieh, Ya-Chun Yu
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Patent number: 11735646Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: GrantFiled: November 6, 2020Date of Patent: August 22, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Patent number: 11515213Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.Type: GrantFiled: January 7, 2021Date of Patent: November 29, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Chung Chen, Po-Chang Lin, Huang-Ren Wei, Wei-Lun Chou
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Publication number: 20220254737Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Publication number: 20220208612Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.Type: ApplicationFiled: January 7, 2021Publication date: June 30, 2022Inventors: Chih-Chung Chen, Po-Chang Lin, Huang-Ren Wei, Wei-Lun Chou
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Patent number: 11348879Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.Type: GrantFiled: September 24, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Patent number: 10965264Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.Type: GrantFiled: May 3, 2019Date of Patent: March 30, 2021Assignee: Rafael Microelectronics, Inc.Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng
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Publication number: 20210057551Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: November 6, 2020Publication date: February 25, 2021Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Publication number: 20210013159Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.Type: ApplicationFiled: September 24, 2020Publication date: January 14, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Patent number: 10868148Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: GrantFiled: December 4, 2018Date of Patent: December 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Publication number: 20200350881Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.Type: ApplicationFiled: May 3, 2019Publication date: November 5, 2020Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng
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Patent number: 10818612Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A semiconductor device having a first surface and a second surface opposite to the first surface is provided. A plurality of through semiconductor vias (TSV) embedded in the semiconductor device is formed. A first seal ring is formed over the first surface of the semiconductor device. The first seal ring is adjacent to edges of the first surface and is physically in contact with the TSVs. A second seal ring is formed over the second surface of the semiconductor device. The second seal ring is adjacent to edges of the second surface and is physically in contact with the TSVs.Type: GrantFiled: April 2, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
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Publication number: 20200331178Abstract: Present invention is related to a microwave and electromagnetic heated foaming method, mold and foaming material thereof. The microwave and electromagnetic heated foaming method comprises steps of adding a foam material into a mold, simultaneously applying a microwave and electromagnetic energy toward the mold under a normal or low pressure, and the microwave and electromagnetic energy made the foam material into molded foam body. The mold of the present invention has a microwave penetrating part and an electromagnetic heating part. The microwave penetrating part has an extruded bottom that is corresponded to a dented top of the electromagnetic heat penetrating part. By utilizing the microwave and electromagnetic energy, the present invention is about to provide an efficient way for processing the foaming material compared to the conventional infrared or electrical heated tube heating and achieve the foam method that can be executed under normal or low pressure.Type: ApplicationFiled: April 15, 2020Publication date: October 22, 2020Inventors: Po-Chang Lin, Kuang-Tse Chin, Jung-Hsiang Hsieh, Ya-Chun Yu
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Publication number: 20200135899Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: December 4, 2018Publication date: April 30, 2020Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh