Abstract: Motor control architecture including a travel, a hoist, and a controller is disclosed. The travel disposed on a main rail having an auxiliary-encoder includes a master-driver and a slave-driver for driving two motors. Each motor has a main-encoder. The hoist drives a rope and calculates a rope length continuously. The controller calculates an anti-sway position command based on the rope-length and a position command. The two drivers perform a full closed-loop computation based on a feedback of one main-encoder, a feedback of the auxiliary-encoder, and the anti-sway position command. Wherein, the master-driver controls one motor based on a speed command generated by the full closed-loop computation and the slave-driver follows the speed command and a torque command of the master-driver to drive another motor; or the two drivers compensate the torque command based on an error value between the feedback of one main-encoder and the feedback of the auxiliary-encoder.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

Abstract: A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.

Abstract: A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

Abstract: The invention provides an RF power amplifier with post-distortion linearizer. The power amplifier includes a main amplifier, an auxiliary amplifier and a phase compensator. The first amplifier has a first input end and a first output end and operates in class A or AB. The auxiliary amplifier has a second input end and a second output end and operates in class B or C. The second output end connects the first output end to form a signal output end. The phase compensator has a third input end and a third output end and compensates a phase difference between the main and auxiliary amplifiers to make outputs of the two amplifiers opposite in phase. The third output end connects the second input end. The third input end connects the first input end to form a signal input end.

Abstract: The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.

Abstract: A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.

Abstract: A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.

Abstract: A liquid crystal display panel including several first electrode portions, several second electrode portions, and a smectic liquid crystal layer is provided. The first electrode portions and the second electrode portions are disposed on a first substrate. When an AC voltage is applied on the first electrode portions and the second electrode portions, the direction of a horizontal electrical field formed between each first electrode portion and the adjacent second electrode portion is parallel to the surface of the first substrate. The smectic liquid crystal layer is interposed between the first substrate and a second substrate. During the phase change of a liquid crystal molecule of the smectic liquid crystal layer, the horizontal electrical field generated by applying the AC voltage on the first electrode portions and the second electrode portions facilitates the alignment of the liquid crystal molecule of the smectic liquid crystal layer.

Abstract: A memory and a voltage monitoring device thereof are provided. the voltage monitoring device of the memory includes a system voltage detector, a charge pump circuit and a data output unit. The system voltage detector is coupled to the charge pump circuit and the data output unit for detecting a system voltage and thereby producing control signals. The charge pump circuit can produce a word line voltage according to the above-mentioned control signals. The data output unit decides outputting the above-mentioned control signals or the output data of the memory according to a special command, wherein the control signals correspond to the word line voltages. Therefore, the control signals and the word line voltages may be easily monitored.

Abstract: A method for manufacturing a transflective LCD panel having a transmissive region and a reflective region includes steps of providing an upper substrate and a lower substrate in parallel, forming a first alignment film on the upper substrate, forming a reflective layer on the reflective region of the lower substrate, forming an first insulating layer to cover the reflective layer and the lower substrate, forming a second insulating layer to cover the first insulating layer, forming positive and negative driving electrodes wrapped in the second insulating layer, forming a coplanar second alignment film to cover the second insulating layer, packaging the upper substrate and the lower substrate, and filling liquid crystal molecules.

Abstract: A method for manufacturing a transflective LCD panel having a transmissive region and a reflective region includes steps of providing an upper substrate and a lower substrate in parallel, forming a first alignment film on the upper substrate, forming a reflective layer on the reflective region of the lower substrate, forming an first insulating layer to cover the reflective layer and the lower substrate, forming a second insulating layer to cover the first insulating layer, forming positive and negative driving electrodes wrapped in the second insulating layer, forming a coplanar second alignment film to cover the second insulating layer, packaging the upper substrate and the lower substrate, and filling liquid crystal molecules.

Abstract: The present invention provides a driving circuit. The driving circuit comprises: a plurality of signal output terminals, a data signal generating module, a gray level reference voltage generating module, a digital-to-analog converter (DAC), a first multiplex output module, an output buffer, a second multiplex output module, and a switch module. The driving circuit of the present invention can reduce the amount of required output buffers, so as to reduce area of the driving circuit efficiently and lower the production cost.

Abstract: A liquid crystal display with transmissive region and reflective region is provided. The display comprises an upper substrate and a lower substrate, which is settled in parallel with the upper substrate. A reflective layer is located on the reflective region of the lower substrate and an insulation layer covers the reflective layer and the lower substrate. Positive and negative driving electrodes are chiastically settled on the insulation layer. A first alignment film is positioned on the inner surface of the upper substrate, and the alignments of the first alignment film on the transmissive region and reflective region are different. A second alignment film covers the insulation layer, the positive and negative electrodes. A liquid crystal layer is located between the first alignment film and the second alignment film.

Abstract: A liquid crystal display panel including several first electrode portions, several second electrode portions, and a smectic liquid crystal layer is provided. The first electrode portions and the second electrode portions are disposed on a first substrate. When an AC voltage is applied on the first electrode portions and the second electrode portions, the direction of a horizontal electrical field formed between each first electrode portion and the adjacent second electrode portion is parallel to the surface of the first substrate. The smectic liquid crystal layer is interposed between the first substrate and a second substrate. During the phase change of a liquid crystal molecule of the smectic liquid crystal layer, the horizontal electrical field generated by applying the AC voltage on the first electrode portions and the second electrode portions facilitates the alignment of the liquid crystal molecule of the smectic liquid crystal layer.

Abstract: The present invention provides a driving circuit. The driving circuit includes: an amount Z of first level shifting units, an amount B of second level shifting units, a first matrix decoding unit, an amount C of third level shifting units, an amount D of fourth level shifting units, a second matrix decoding unit, and a third matrix decoding unit. The driving circuit can generate an amount (Z×B)×(C×D) of high voltage digital output signals. The driving circuit provided by the present invention can significantly decrease the required high voltage elements (i.e. the level shifting units), and thus the present invention can reduce area of the driving circuit efficiently.

Abstract: An LCD panel including a first substrate, a second substrate and a smectic liquid crystal layer is disclosed. The first substrate includes a first electrode, a second electrode and a first horizontal alignment film. The first electrode has plural first portions. The second electrode has plural second portions. The first portions are spaced by the second portions. The electrical field directions formed between the first portions and the second portions are perpendicular to the surface of the first substrate. The electrical field direction on each first portion is opposite to that on each second portion. The first horizontal alignment film covers the first and the second electrodes. The second substrate includes a second horizontal alignment film. The horizontal rubbing direction of the first horizontal alignment film is parallel to that of the second horizontal alignment film. The smectic liquid crystal layer is sealed between the first and the second substrates.

Abstract: A liquid crystal display panel including several first electrode portions, several second electrode portions, and a smectic liquid crystal layer is provided. The first electrode portions and the second electrode portions are disposed on a first substrate. When an AC voltage is applied on the first electrode portions and the second electrode portions, the direction of a horizontal electrical field formed between each first electrode portion and the adjacent second electrode portion is parallel to the surface of the first substrate. The smectic liquid crystal layer is interposed between the first substrate and a second substrate. During the phase change of a liquid crystal molecule of the smectic liquid crystal layer, the horizontal electrical field generated by applying the AC voltage on the first electrode portions and the second electrode portions facilitates the alignment of the liquid crystal molecule of the smectic liquid crystal layer.

Abstract: A memory and a voltage monitoring device thereof are provided. the voltage monitoring device of the memory includes a system voltage detector, a charge pump circuit and a data output unit. The system voltage detector is coupled to the charge pump circuit and the data output unit for detecting a system voltage and thereby producing control signals. The charge pump circuit can produce a word line voltage according to the above-mentioned control signals. The data output unit decides outputting the above-mentioned control signals or the output data of the memory according to a special command, wherein the control signals correspond to the word line voltages. Therefore, the control signals and the word line voltages may be easily monitored.