Patents by Inventor Po-Chen Lin

Po-Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200167752
    Abstract: Obtain first item data from a first client system coupled to a central server system. Identify a first modification object associated with the first item data. Provide the first modification object to the first client system. Obtain a user identifier from the first client system. Identify a first user associated with the user identifier as being eligible to receive the first modification object. Provide a first eligibility message to the first client system. Obtain second item data from a second client system coupled to the central server system. Identify a second modification object associated with the second item data. Provide the second modification object to the second client system. Obtain the user identifier from the second client system. Identify a second user associated with the user identifier as being eligible to receive the second modification object. Provide a second eligibility message to the second client system.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 28, 2020
    Applicant: SKUPOS Inc.
    Inventors: Nam Nguyen, Richard Woolsey, Po Chen Lin, Jacob Bolling, Zachary Kimball, Michael Glassman
  • Publication number: 20190303756
    Abstract: A method of training a neural network including multiple neural network weights and multiple neurons, and the method includes using floating-point signed digit numbers to represent each of the multiple neural network weights, wherein a mantissa of each of the multiple neural network weights is represented by multiple mantissa signed digit groups and an exponent of each of the multiple neural network weights is represented by an exponent digit group; and using the exponent digit group and at least one of the multiple mantissa signed digit groups to perform weight adjustment computation and neural network inference computation.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 3, 2019
    Inventors: Tzi-Dar Chiueh, Po-Chen Lin
  • Publication number: 20190295984
    Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
    Type: Application
    Filed: February 22, 2019
    Publication date: September 26, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Po-Chen Lin, Ra-Min Tain, Chun-Hsien Chien, Chien-Chou Chen
  • Patent number: 9484315
    Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 1, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
  • Patent number: 9412323
    Abstract: The present disclosure provides a power saving method for a LCD comprising a plurality of scan lines. The power saving method comprises segregating the scan lines into a plurality of scan line groups; and individually performing a waveform-shaping function on each of the scan-line groups at different time points.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 9, 2016
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chiu-Hung Cheng, Po-Chen Lin
  • Publication number: 20160163665
    Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
    Type: Application
    Filed: March 26, 2015
    Publication date: June 9, 2016
    Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
  • Patent number: 9208711
    Abstract: An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 8, 2015
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chien-Chia Shih, Feng-Ting Pai, Po-Chen Lin, Shih-Hung Huang
  • Publication number: 20150091885
    Abstract: The present disclosure provides a power saving method for a LCD comprising a plurality of scan lines. The power saving method comprises segregating the scan lines into a plurality of scan line groups; and individually performing a waveform-shaping function on each of the scan-line groups at different time points.
    Type: Application
    Filed: January 16, 2014
    Publication date: April 2, 2015
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chiu-Hung Cheng, Po-Chen Lin
  • Publication number: 20120299904
    Abstract: An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data.
    Type: Application
    Filed: April 3, 2012
    Publication date: November 29, 2012
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chien-Chia SHIH, Feng-Ting Pai, Po-Chen Lin, Shih-Hung Huang
  • Patent number: 6612724
    Abstract: A lampshade has a frame and a shade. The frame has an upper collar, a lower collar and multiple supporting frames. The upper collar is attached to the stand of the lamp. The supporting frames are detachably mounted between the upper collar and the lower collar. Each supporting frame has an upper section, two side rods and a lower section. The lower section is connected to the side rods at the end far away from the upper section. The lower section abuts against the top of the lower collar. Such a lampshade can be disassembled into multiple parts whereby it is detachable to reduce the lampshade in size. Thus, to store and to transport the lampshade are convenient.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: September 2, 2003
    Inventor: Po-Chen Lin
  • Publication number: 20030123256
    Abstract: A lampshade has a frame and a shade. The frame has an upper collar, a lower collar and multiple supporting frames. The upper collar is attached to the stand of the lamp. The supporting frames are detachably mounted between the upper collar and the lower collar. Each supporting frame has an upper section, two side rods and a lower section. The lower section is connected to the side rods at the end far away from the upper section. The lower section abuts against the top of the lower collar. Such a lampshade can be disassembled into multiple parts whereby it is detachable to reduce the lampshade in size. Thus, to store and to transport the lampshade are convenient.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventor: Po-Chen Lin