Patents by Inventor Po-Cheng LAI

Po-Cheng LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277326
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The memory device may be arranged to receive a set of first commands, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, and determine a selected table update size among multiple predetermined table update sizes such as multiple table entry counts and update at least one logical-to-physical address mapping table according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, where the table update size may be dynamically changed for enhancing overall performance.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: April 15, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Keng-Yuan Hsu, Po-Cheng Lai
  • Publication number: 20250068336
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The method may include: utilizing a memory controller to receive a set of first commands from a host device, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block; determining a selected table update size among multiple predetermined table update sizes according to at least one predetermined rule, wherein the multiple predetermined table update sizes represent multiple table entry counts, respectively; and updating at least one logical-to-physical address mapping table in the NV memory according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, for further data accessing.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Keng-Yuan Hsu, Po-Cheng Lai
  • Publication number: 20240320095
    Abstract: A method for performing table management of a memory device in predetermined communications architecture with aid of flexible table page grouping and associated apparatus are provided. The method may include: utilizing the memory controller to perform a table management procedure to manage at least one table regarding internal management of the memory device. For example, the table management procedure may include: in response to updating a first previous table content of a first table among the at least one table being needed, writing a first updated table content of the first table into at least one first updated table page of at least one table block; and writing a first RAID parity of the first updated table content into a first parity page, wherein a first updated table page count of the at least one first updated table page protected by the first parity page is determined in real time.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Jie-Hao LEE, Keng-Yuan HSU, Po-Cheng LAI
  • Patent number: 12087579
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Patent number: 11967272
    Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 23, 2024
    Assignees: AUO Corporation, National Cheng-Kung University
    Inventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
  • Publication number: 20240029630
    Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.
    Type: Application
    Filed: December 9, 2022
    Publication date: January 25, 2024
    Applicants: AUO Corporation, National Cheng-Kung University
    Inventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
  • Patent number: 11495155
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 8, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Patent number: 11289013
    Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: March 29, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Po-Cheng Lai, Ting-Ching Chu, Po-Chun Lai, Mao-Hsun Cheng
  • Publication number: 20210255542
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: CHUNG-YANG HUANG, HAO-MING CHANG, MING CHE LI, YU-HSIN HSU, PO-CHENG LAI, KUAN-SHIEN LEE, WEI-HSIN LIN, YI-HSUAN LIN, WANG CHENG SHIH, CHENG-MING LIN
  • Patent number: 11036129
    Abstract: A method for forming a photomask includes receiving a substrate having a first layer formed thereon, wherein a patterned second layer exposing portions of the first layer is disposed over the substrate, removing the exposed portions of the first layer through the patterned second layer to form a plurality of openings in the first layer, removing the patterned second layer, and performing a wet etching to remove portions of the first layer to widen the plurality of openings with an etchant. The etchant is in contact with a top surface of the first layer and sidewalls of the plurality of openings. Each of the plurality of openings has a first width prior to the performing of the wet etching and a second width after the performing of the wet etching. The second width is greater than the first width.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Publication number: 20210125547
    Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 29, 2021
    Inventors: Chih-Lung LIN, Po-Cheng LAI, Ting-Ching CHU, Po-Chun LAI, Mao-Hsun CHENG
  • Patent number: 10964245
    Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 30, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Po-Cheng Lai, Mao-Hsun Cheng, Cheng-Han Huang, Yung-Chih Chen, Ching-Sheng Cheng, Chih-Lung Lin
  • Publication number: 20210074195
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Patent number: 10916169
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: February 9, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Publication number: 20200294436
    Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.
    Type: Application
    Filed: October 15, 2019
    Publication date: September 17, 2020
    Inventors: Po-Cheng LAI, Mao-Hsun CHENG, Cheng-Han HUANG, Yung-Chih CHEN, Ching-Sheng CHENG, Chih-Lung LIN
  • Publication number: 20200047393
    Abstract: A blow molding machine suitable for manufacturing the bottle having the handle and a method for using the same, wherein each of the preform holders has a local temperature regulating device, the local temperature regulating devices are disposed around the handle portion, the rotary joint supplies liquid or gas continuously to the local temperature regulating devices of the preform holders to perform continuous temperature regulation for the handle portion, thereby overcoming the problem that the temperature needs to be immediately cooled after the injection molding, and temperature of the body portion can be maintained, so as to achieve the purpose of reducing energy consumption.
    Type: Application
    Filed: August 12, 2018
    Publication date: February 13, 2020
    Inventors: WEN-YUNG YANG, SHU-LIN HSIEH, HUAI-RONG PAN, ZHI-ZHONG LUO, PO-CHENG LAI
  • Publication number: 20200041894
    Abstract: A method for forming a photomask includes receiving a substrate having a first layer formed thereon, wherein a patterned second layer exposing portions of the first layer is disposed over the substrate, removing the exposed portions of the first layer through the patterned second layer to form a plurality of openings in the first layer, removing the patterned second layer, and performing a wet etching to remove portions of the first layer to widen the plurality of openings with an etchant. The etchant is in contact with a top surface of the first layer and sidewalls of the plurality of openings. Each of the plurality of openings has a first width prior to the performing of the wet etching and a second width after the performing of the wet etching. The second width is greater than the first width.
    Type: Application
    Filed: December 6, 2018
    Publication date: February 6, 2020
    Inventors: CHUNG-YANG HUANG, HAO-MING CHANG, MING CHE LI, YU-HSIN HSU, PO-CHENG LAI, KUAN-SHIEN LEE, WEI-HSIN LIN, YI-HSUAN LIN, WANG CHENG SHIH, CHENG-MING LIN
  • Publication number: 20190385503
    Abstract: A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 19, 2019
    Inventors: Chih-Lung Lin, Chin-Hsien Tseng, Po-Cheng Lai, Yu-Sheng Lin, Mao-Hsun Cheng
  • Patent number: 10175098
    Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chih-Lung Lin, Chia-En Wu, Po-Syun Chen, Fu-Hsing Chen, Ming-Xun Wang, Ching-En Lee, Po-Cheng Lai, Jian-Shen Yu
  • Patent number: 9908278
    Abstract: A blow molding device for a rotary bottle blowing machine includes: a support base including a power-input shaft and a mold-insert control shaft which are pivotally disposed on the support base and extend along an axial direction; a drive source for driving the power-input shaft and the mold-insert control shaft to rotate; and a mold assembly with a first and second movable mold inserts pivotally disposed on the support base. The mold assembly makes the first and second movable mold inserts pivot toward or away from each other, rotation of the power-input shaft makes a bottom mold unit move in the axial direction, and can lock the first and second movable mold inserts. A method for using the blow molding device includes steps of mold opening or closing, mold lifting, and mold locking, and these steps are performed by using a single drive source.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: March 6, 2018
    Assignee: CHUMPOWER MACHINERY CORP.
    Inventors: Wen-Yung Yang, Po-Cheng Lai, Xuan-Quyen Nguyen, Zhi-Zhong Luo, Jin-Ge Zhang, Huai-Rong Pan, Shu-Lin Xie