Patents by Inventor Po-Cheng Wang
Po-Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153824Abstract: A method includes forming a stack of channel layers and sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, and recessing a portion of the fin-shape structure to form a recess. A top surface of the substrate under the recess is covered at least by a bottommost sacrificial layer of the stack. The method also includes forming inner spacers on terminal ends of the sacrificial layers that are above the bottommost sacrificial layer, depositing an undoped layer in the recess, and forming a doped epitaxial feature over the undoped layer. The undoped layer covers terminal ends of a bottommost channel layer of the stack. The doped epitaxial feature covers terminal ends of the channel layers that are above the bottommost channel layer.Type: ApplicationFiled: March 22, 2023Publication date: May 9, 2024Inventors: Ting-Yeh CHEN, Wei-Yang LEE, Po-Cheng WANG, De-Fang CHEN, Chao-Cheng CHEN
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Publication number: 20240152880Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.Type: ApplicationFiled: February 13, 2023Publication date: May 9, 2024Applicant: OBOOK INC.Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
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Publication number: 20240154022Abstract: A method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the fin structures, and wherein a space is located between the fin structures and above the isolation region; depositing a blocking layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the blocking layer is located above the first fin structure and the second fin structure, and wherein a lower portion of the blocking layer fills the space located between the first fin structure and the second fin structure; removing the upper portion of the blocking layer; and while the lower portion of the blocking layer remains over the isolation region, performing an etch process to recess the first fin structure and the second fin structure.Type: ApplicationFiled: February 7, 2023Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Ho, Po-Cheng Wang, De-Fang Chen, Chao-Cheng Chen
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Publication number: 20240153840Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
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Publication number: 20240144098Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.Type: ApplicationFiled: October 16, 2023Publication date: May 2, 2024Applicant: MEDIATEK INC.Inventors: Chao Peng WANG, Chia-Da LEE, Po-Yu CHEN, Hsiao-Chien CHIU, Yi-Cheng LU
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Publication number: 20240096731Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
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Publication number: 20240096997Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed in a PFET region and a second source/drain region disposed in an NFET region. The second source/drain region comprises a dipole region. The structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. The first, second, and third silicide layers include different materials. The structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.Type: ApplicationFiled: January 15, 2023Publication date: March 21, 2024Inventors: Po-Chin Chang, Lin-Yu Huang, Li-Zhen Yu, Yuting Cheng, Sung-Li Wang, Pinyen Lin
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Publication number: 20240079267Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Publication number: 20240074826Abstract: A surgical robot including at least one contact module, a control connection module, at least one first robotic arm, and at least one grip control device. A first transmission member of the control connection module drives the control module through a first transmission connecting member. A first shaft member of the first robotic arm is connected with the first transmission member while the grip control device is connected with the first robotic arm by a transmission interface. A force sensing member of the first robotic arm detects a first reaction force from the contact module so that the first robotic arm sends a feedback control signal to the grip control device to control a grip driving member to generate a force feedback for allowing a grip portion to move. Thereby, users can feel movement of the grip portion caused by the force feedback to avoid accidental iatrogenic injuries.Type: ApplicationFiled: September 14, 2022Publication date: March 7, 2024Inventors: PO-YUN LIU, CHUN-HUNG KUO, CHIH-CHENG CHIEN, YEN-CHIEH WANG
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Patent number: 11923034Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.Type: GrantFiled: December 23, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang
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Patent number: 11915992Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.Type: GrantFiled: February 24, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
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Publication number: 20240057240Abstract: A light control device, a control method, and a server thereof are provided. The light control device includes a first controller and a second controller. The first controller is disposed on a first circuit board. The first controller is coupled to a selected signal source of multiple signal sources, re-encodes a received control signal, and transmits an encoded control signal through a transmission interface. The second controller is disposed on a second circuit board. The second controller decodes the encoded control signal to generate multiple driving signals. The driving signals are respectively for driving and controlling lighting statuses of multiple lighting components.Type: ApplicationFiled: October 18, 2022Publication date: February 15, 2024Applicant: Wistron CorporationInventors: Chin Tsan Wang, Yu Chang Liu, Po Cheng Wang
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Patent number: 11855167Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.Type: GrantFiled: July 8, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng Wang, Ting-Yeh Chen, De-Fang Chen, Wei-Yang Lee
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Publication number: 20230020731Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.Type: ApplicationFiled: November 23, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
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Publication number: 20230010717Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng WANG, Ting-Yeh CHEN, De-Fang CHEN, Wei-Yang LEE
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Patent number: 9742145Abstract: A high-efficiency non-collinearly phase matched parametric oscillator is provided, wherein a laser pumps a nonlinear optical material with a plural number of flat reflection surfaces that zigzag at least one parametrically generated off-axis radiation about the pump laser beam axis via multiple reflections from the surfaces. The off-axis zigzag oscillation of the radiation establishes parametric oscillation and improves energy coupling among mixing waves in a monolithic nonlinear optical material. Preferably the pump laser has a transverse beam size covering the area of the zigzagging parametrically generated radiation. To further enhance the performance of the off-axis zigzag parametric oscillator, the other parametrically generated radiation can be seeded by an external laser source or resonated in a cavity. The present invention also includes a double-side pumped off-axis zigzag parametric oscillator installed inside a standing-wave pump-laser cavity.Type: GrantFiled: December 1, 2016Date of Patent: August 22, 2017Assignee: National Tsing Hua UniversityInventors: Yen-Chieh Huang, Tsong-Dong Wang, Yu-Chung Chiu, Po-Cheng Wang
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Patent number: 8065712Abstract: Methods and devices for qualifying a client machine to access a network, based on policies governing required protective measures, such as virus checking and operating system updates, are disclosed. A client machine must pass various checks to qualify for access. A client machine may be redirected to remediation resources that support efforts to bring the client machine into compliance with applicable network access requirements. A policy repository is updated regularly by vendors of protective measures. An administrator establishes user roles that are mapped to policy rule sets retrieved from the policy repository. The policy rule sets govern qualification of client machines for access to the network in accordance with the roles of the users of the machines. An access server is an intermediary between a client machine and the access manager. A client agent runs on the client machine and carries out checks, and reports the results via the access server to the access manager.Type: GrantFiled: May 25, 2005Date of Patent: November 22, 2011Assignee: Cisco Technology, Inc.Inventors: Wen-Chun Cheng, Po-Cheng Wang, Venkatapathi Raju Srirajavatchavai, Rajesh Nair
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Patent number: 8005049Abstract: The present invention relates to methods and devices that support mobility of a client across a campus, particularly mobility across VLANs and subnets, while preserving the client's assigned IP address. Both layer 2 and layer 3 packets are supported. Mobility support most clearly applies to wireless clients, but could apply to other kinds of mobile connections, even to wired connections. A smart server is adapted to support multiple VLANs and to modify and redirect packets in sessions with a client that moves from one VLAN to another, preserving the client's assigned EP address. Two or more smart servers, in cooperation with a smart manger, modify packets and tunnel them between smart servers when a client that moves from one VLAN to another and from one smart server to another, again preserving the client's assigned IF address.Type: GrantFiled: April 12, 2010Date of Patent: August 23, 2011Assignee: Cisco Technology, Inc.Inventors: Wen-Chun Cheng, Po-Cheng Wang, Rajesh Nair
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Publication number: 20100195620Abstract: The present invention relates to methods and devices that support mobility of a client across a campus, particularly mobility across VLANs and subnets, while preserving the client's assigned IP address. Both layer 2 and layer 3 packets are supported. Mobility support most clearly applies to wireless clients, but could apply to other kinds of mobile connections, even to wired connections. A smart server is adapted to support multiple VLANs and to modify and redirect packets in sessions with a client that moves from one VLAN to another, preserving the client's assigned EP address. Two or more smart servers, in cooperation with a smart manger, modify packets and tunnel them between smart servers when a client that moves from one VLAN to another and from one smart server to another, again preserving the client's assigned IF address.Type: ApplicationFiled: April 12, 2010Publication date: August 5, 2010Inventors: Wen-Chun Cheng, Po-Cheng Wang, Rajesh Nair
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Patent number: 7720031Abstract: The present invention relates to methods and devices that support mobility of a client across a campus, particularly mobility across VLANs and subnets, while preserving the client's assigned IP address. Both layer 2 and layer 3 packets are supported. Mobility support most clearly applies to wireless clients, but could apply to other kinds of mobile connections, even to wired connections. A smart server is adapted to support multiple VLANs and to modify and redirect packets in sessions with a client that moves from one VLAN to another, preserving the client's assigned IP address. Two or more smart servers, in cooperation with a smart manger, modify packets and tunnel them between smart servers when a client that moves from one VLAN to another and from one smart server to another, again preserving the client's assigned IP address.Type: GrantFiled: October 15, 2004Date of Patent: May 18, 2010Assignee: Cisco Technology, Inc.Inventors: Wen-Chun Cheng, Po-Cheng Wang, Rajesh Nair