Patents by Inventor Po-Chi Hsieh

Po-Chi Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device packages having stacking functionality and including interposer
    Patent number: 8823156
    Abstract: A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Po-Chi Hsieh
  • SEMICONDUCTOR DEVICE PACKAGES HAVING STACKING FUNCTIONALITY AND INCLUDING INTERPOSER
    Publication number: 20110193205
    Abstract: A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Inventor: Po-Chi Hsieh