Patents by Inventor Pochi Wu

Pochi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating gate structures
    Patent number: 8030214
    Abstract: An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl2.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochi Wu, Ju-Wang Hsu, Ryan Chia-Jen Chen
  • METHOD OF FABRICATING GATE STRUCTURES
    Publication number: 20110207315
    Abstract: An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl2.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 25, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochi WU, Ju-Wang Hsu, Ryan Chia-Jen Chen