Patents by Inventor Po-Chia CHEN

Po-Chia CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978676
    Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Po-Kang Ho, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11960253
    Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 16, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu Huang, Chun-Fang Chen, Hong-Chi Ku, Te-Ming Chen, Chien-Liang Lai, Sen-Chia Chang
  • Publication number: 20240112912
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Patent number: 11656980
    Abstract: Disclosed herein is an extensible memory subsystem comprising a dual in-line memory module (DIMM) that includes a dynamic random-access memory (DRAM) having a basic memory space, a DIMM memory controller coupled to the DRAM, a memory interface configured to couple the DIMM to a DIMM connector of a computing device, and a first extension interface configured to couple the DIMM to a first remote memory module having a first remote memory space, wherein the DIMM memory controller is configured to map a DIMM memory space comprising the basic memory space of the DRAM and the first remote memory space of the first remote memory module, the DIMM memory space being accessible by the computing device upon the DIMM being coupled to the computing device via the memory interface, and a first remote memory module coupled to the DIMM via the first extension interface of the DIMM.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 23, 2023
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Yu-Wei Hsieh, Po Chia Chen, Li-Ping Zhang, Tai Wei Hsia
  • Publication number: 20210109849
    Abstract: Disclosed herein is an extensible memory subsystem comprising a dual in-line memory module (DIMM) that includes a dynamic random-access memory (DRAM) having a basic memory space, a DIMM memory controller coupled to the DRAM, a memory interface configured to couple the DIMM to a DIMM connector of a computing device, and a first extension interface configured to couple the DIMM to a first remote memory module having a first remote memory space, wherein the DIMM memory controller is configured to map a DIMM memory space comprising the basic memory space of the DRAM and the first remote memory space of the first remote memory module, the DIMM memory space being accessible by the computing device upon the DIMM being coupled to the computing device via the memory interface, and a first remote memory module coupled to the DIMM via the first extension interface of the DIMM.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 15, 2021
    Inventors: Yu-Wei Hsieh, Po Chia Chen, Li-Ping Zhang, Tai Wei Hsia
  • Patent number: 10522369
    Abstract: A method of cleaning a wafer in semiconductor fabrication is provided. The method includes cleaning a wafer using a wafer scrubber. The method further includes moving the wafer scrubber into an agitated cleaning fluid. The method also includes creating a contact between the wafer scrubber and a cleaning stage in the agitated cleaning fluid. In addition, the method includes cleaning the wafer or a second wafer by the wafer scrubber after the wafer scrubber is cleaned by the agitated cleaning fluid.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chun Hu, Chen-Liang Chang, Ju-Ru Hsieh, Po-Chia Chen, Shun-Yu Chuang, Wei-Tuzo Lin
  • Patent number: 9536757
    Abstract: A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Po Chia Chen, Kuo-Sheng Chuang, Chi-Ming Yang
  • Publication number: 20160254170
    Abstract: A method of cleaning a wafer in semiconductor fabrication is provided. The method includes cleaning a wafer using a wafer scrubber. The method further includes moving the wafer scrubber into an agitated cleaning fluid. The method also includes creating a contact between the wafer scrubber and a cleaning stage in the agitated cleaning fluid. In addition, the method includes cleaning the wafer or a second wafer by the wafer scrubber after the wafer scrubber is cleaned by the agitated cleaning fluid.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Chien-Chun HU, Chen-Liang CHANG, Ju-Ru HSIEH, Po-Chia CHEN, Shun-Yu CHUANG, Wei-Tuzo LIN
  • Publication number: 20150068559
    Abstract: A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Po Chia Chen, Kuo-Sheng Chuang, Chi-Ming Yang
  • Patent number: D1027182
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 14, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Ming Cheng, Chih-Lin Liao, Yi-Chia Chiu, Chun-Ta Chen, Po-Lun Chen