Patents by Inventor Po-Chien Chiang

Po-Chien Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978496
    Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Patent number: 11973501
    Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 30, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Patent number: 11881255
    Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 23, 2024
    Assignee: NVIDIA CORP.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, Chunjen Su
  • Publication number: 20230352081
    Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: NVIDIA Corp.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, CHUNJEN SU
  • Publication number: 20230353155
    Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: NVIDIA Corp.
    Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Publication number: 20230352077
    Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: NVIDIA Corp.
    Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
  • Publication number: 20230352078
    Abstract: The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: NVIDIA Corp.
    Inventors: Jiwang Lee, Jaewon Lee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Hsuche Nee, Po-Chien Chiang