Patents by Inventor Po-Chih Su

Po-Chih Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200273982
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10686065
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10680100
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Publication number: 20200169708
    Abstract: A projection apparatus and its operation method are provided. The projection apparatus includes a light-emitting device, a driving circuit coupled to the light-emitting device, and a control circuit receiving at least one video frame and analyzing color content of the at least one video frame. According to at least one control signal, the driving circuit drives the light-emitting device to generate a projected beam. The control circuit selects a highlight mode or a normal mode as a selected mode according to the color content and correspondingly sets at least one control signal to the driving circuit according to the selected mode. A brightness of the projected beam of the light-emitting device in the highlight mode is greater than that in the normal mode.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 28, 2020
    Applicant: Coretronic Corporation
    Inventors: Wei-Chih Su, Sheng-Yu Chiu, Po-Yen Wu, Jung-Chi Chen, Chih-Lin Wang
  • Patent number: 10636904
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20200044014
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200020802
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10535730
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200013888
    Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu
  • Publication number: 20200006489
    Abstract: A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hsueh-Liang Chou, Chun-Wai Ng, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10510880
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Publication number: 20190267377
    Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10304829
    Abstract: A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190109229
    Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Publication number: 20190051745
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10170589
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 10164085
    Abstract: A method comprises forming a buried layer over a substrate, forming an epitaxial layer over the buried layer, forming a first trench and a second trench in the buried layer and the epitaxial layer, wherein a width of the second trench is greater than a width of the first trench, depositing a dielectric layer in the first trench and the second trench, wherein the dielectric layer partially fills the second trench, removing the dielectric layer in the second trench and forming a first gate region in the first trench and a second gate region in the second trench.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10141421
    Abstract: A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected. The region between the first and the second gate electrodes overlaps the doped semiconductor region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10109732
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 10090390
    Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu