Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract: The present disclosure relates an integrated chip structure. The integrated chip structure includes a first chiplet predominantly having a first plurality of integrated chip devices coupled to a first plurality of interconnects over a first substrate. The first plurality of integrated chip devices are a first type of integrated chip device. The integrated chip structure further includes a second chiplet predominantly having a second plurality of integrated chip devices coupled to a second plurality of interconnects over a second substrate. The second plurality of integrated chip devices are a second type of integrated chip device different than the first type of integrated chip device. One or more inter-chiplet connectors are between the first and second chiplets and are configured to electrically couple the first and second chiplets. The first plurality of interconnects have a first minimum width different than a second minimum width of the second plurality of interconnects.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Abstract: A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.

Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.

Abstract: A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.