Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchial search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.

Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.

Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.

Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchical search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.

Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay.