Patents by Inventor Po-Chih Yang

Po-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096822
    Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230290684
    Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Wei Chang Wong, Radhakrishna Kotti, Raj K. Bansal, Youngik Kwon, Po Chih Yang, Venkateswarlu Bhavanasi
  • Patent number: 11705421
    Abstract: Semiconductor devices including continuous-core connectors and associated systems and methods are disclosed herein. The continuous-core connectors each include a peripheral wall that surrounds an inner-core configured to provide an electrical path using uniform material.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Po Chih Yang, Po Chen Kuo, Chih Hong Wang
  • Publication number: 20220352025
    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventor: Po Chih Yang
  • Publication number: 20220336397
    Abstract: Semiconductor devices including continuous-core connectors and associated systems and methods are disclosed herein. The continuous-core connectors each include a peripheral wall that surrounds an inner-core configured to provide an electrical path using uniform material.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Po Chih Yang, Po Chen Kuo, Chih Hong Wang
  • Patent number: 11393720
    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Po Chih Yang
  • Publication number: 20220208713
    Abstract: A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.
    Type: Application
    Filed: June 9, 2021
    Publication date: June 30, 2022
    Inventors: Jong Sik Paek, Po Chih Yang
  • Publication number: 20220037282
    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 3, 2022
    Inventors: Po Chih Yang, Yu Jen Chen, Po Chen Kuo, Shih Wei Liang
  • Publication number: 20210391216
    Abstract: A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventor: Po Chih Yang
  • Patent number: 11171109
    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Po Chih Yang, Yu Jen Chen, Po Chen Kuo, Shih Wei Liang
  • Publication number: 20210091036
    Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Po Chih Yang, Yu Jen Chen, Po Chen Kuo, Shih Wei Liang
  • Publication number: 20050207101
    Abstract: A display device includes a base, a display unit having a display screen, a support mounted on the base to support the display unit, and a slide mechanism provided on a back panel of the display screen. The support is connected to the slide mechanism so that the display unit is slidable and pivotable relative to the support. The support may include a link unit and an arm unit both of which are rotatable relative to the base. Further, the arm unit is connected to the slide mechanism and is rotatable and slidable relative to the display unit.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 22, 2005
    Inventors: I-Pin Hwang, Hsing-Yeu Chang, Lin-Ming Chen, Chun-Leung Choi, Po-Chih Yang
  • Patent number: D504892
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 10, 2005
    Assignee: Chi Lin Technology Co., Ltd.
    Inventors: Lin-Ming Chen, Chun-Leung Choi, Po-Chih Yang, I-Pin Hwang