Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A feature extraction process is performed to obtain features based on the LDR images and the HDR images. A second neural network for video stabilization is trained according to the LDR images and the HDR images based on a loss function by minimizing a loss value of the loss function to generate stabilized HDR images in a time-dependent manner, where the loss value of the loss function depends upon the features. An HDR classifier is constructed according to the LDR images and the HDR images. The stabilized HDR images are classified by using the HDR classifier to generate a reward value, where the loss value of the loss function further depends upon the reward value.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A feature extraction process is performed to obtain features based on the LDR images and the HDR images. A second neural network for video stabilization is trained according to the LDR images and the HDR images based on a loss function by minimizing a loss value of the loss function to generate stabilized HDR images in a time-dependent manner, where the loss value of the loss function depends upon the features. An HDR classifier is constructed according to the LDR images and the HDR images. The stabilized HDR images are classified by using the HDR classifier to generate a reward value, where the loss value of the loss function further depends upon the reward value.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.

Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Abstract: An image data processing method is provided. In this method, a plurality of original pixel values of an image is input. An interpolation position of a target pixel in the image is determined. Whether the interpolation position is in a central region of an object or in a marginal region of an object is determined. A pixel value interpolation with respect to the interpolation position is performed. When the interpolation position is in the central region of an object, the pixel value interpolation is performed in a first calculation mode, and when the interpolation position is in the marginal region of an object, the pixel value interpolation is performed in a second calculation mode, wherein the first calculation mode may be a low pass filtering interpolation mode, and the second calculation mode may be a linear interpolation mode.

Abstract: A method for image compression coding is provided. According to the method, a plurality of codebooks is created according to the correlation between pixels, and the quantization value of each state is determined by dynamically looking up the codebooks. Therefore, the present invention not only enhances the image compression ratio but also improves the image compression quality.

Abstract: A method of block encoding of an image includes partitioning an image into a plurality of blocks each having a plurality of pixels corresponding to a first matrix, obtaining a first block from the plurality of blocks, rearranging pixels of the first block for generating a second block according to an arrangement rule, performing wavelet transformation for the second block for generating a third block having a plurality of wavelet coefficients corresponding to the first matrix, rearranging the wavelet coefficients of the third block for generating a fourth block according to the arrangement rule, quantizing the fourth block, and encoding a quantized result of the fourth block.

Abstract: The present invention discloses a method for compressing and decompressing pixel data and the device thereof. The method comprises receiving current pixel data from a preprocessor and comparing the current pixel data with predictor pixel data to obtain a section index from a quantization table. Output the section index to a memory as compressed data. Then, receive the compressed data from the memory. Use the quantization table to look up a representative level corresponding to the compressed data and output decompressed pixel data based on the representative level to an image processing unit. The device mentioned above comprises a memory, a compressor and a decompressor. The memory stores compressed data. The compressor quantizes and compresses pixel data and outputs the compressed pixel data to the memory. The decompressor receives the compressed pixel data and decompresses the compressed pixel data and outputs the decompressed pixel data as pixel data.

Abstract: An image data processing method is provided. In this method, a plurality of original pixel values of an image is input. An interpolation position of a target pixel in the image is determined. Whether the interpolation position is in a central region of an object or in a marginal region of an object is determined. A pixel value interpolation with respect to the interpolation position is performed. When the interpolation position is in the central region of an object, the pixel value interpolation is performed in a first calculation mode, and when the interpolation position is in the marginal region of an object, the pixel value interpolation is performed in a second calculation mode, wherein the first calculation mode may be a low pass filtering interpolation mode, and the second calculation mode may be a linear interpolation mode.

Abstract: A method for image compression coding is provided. According to the method, a plurality of codebooks is created according to the correlation between pixels, and the quantization value of each state is determined by dynamically looking up the codebooks. Therefore, the present invention not only enhances the image compression ratio but also improves the image compression quality.