Abstract: A semiconductor device includes a substrate, a power device, a protection circuit, a dielectric layer, a drain pad, a source pad, and a gate pad. The power device and the protection circuit are disposed on the substrate. The power device includes a drain electrode, a source electrode, and a gate electrode. The protection circuit has a first terminal electrically connected with the source pad and a second terminal electrically connected with the gate pad. The dielectric layer is disposed on the power device and the protection circuit. The drain pad, the source pad, and the gate pad are disposed on the dielectric layer and respectively electrically connected with the drain electrode, the source electrode, and the gate electrode. At least part of the protection circuit is disposed under the source pad, the gate pad, or the drain pad.

Abstract: A semiconductor device including a substrate, a plurality of III-nitride semiconductor layers, a source electrode, a gate electrode, a drain electrode, and a doped layer. The III-nitride semiconductor layers are disposed on the substrate. A two dimensional electron gas (2DEG) channel is formed in the III-nitride semiconductor layers. The source electrode, the gate electrode, and the drain electrode are disposed on the III-nitride semiconductor layers. The gate electrode is located between the source electrode and the drain electrode. The source electrode and the drain electrode are electrically connected to the 2DEG channel. A lateral direction is defined from the source electrode to the drain electrode. The doped layer is disposed between the gate electrode and the III-nitride semiconductor layers. The doped layer includes a plurality of dopants, and a concentration of the dopants varies along the lateral direction.

Abstract: A semiconductor device includes a substrate, a power device, a protection circuit, a dielectric layer, a drain pad, a source pad, and a gate pad. The power device and the protection circuit are disposed on the substrate. The power device includes a drain electrode, a source electrode, and a gate electrode. The protection circuit has a first terminal electrically connected with the source pad and a second terminal electrically connected with the gate pad. The dielectric layer is disposed on the power device and the protection circuit. The drain pad, the source pad, and the gate pad are disposed on the dielectric layer and respectively electrically connected with the drain electrode, the source electrode, and the gate electrode. At least part of the protection circuit is disposed under the source pad, the gate pad, or the drain pad.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.