Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: The disclosure provides a local stretch packaging structure, including a substrate, a flexible electronic element, a plurality of light-emitting display elements, and a packaging layer. The flexible electronic element is disposed on the substrate. These light-emitting display elements are disposed on the flexible electronic element. The packaging layer includes a packaging area and a non-packaging area. The packaging area covers the upper surface and sidewalls of these light-emitting display elements. The non-packaging area is directly covered the flexible electronic element that is not disposed with these light-emitting display elements.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: An image processing method includes obtaining a sensed image, wherein the sensed image comprises a pattern; dividing the sensed image into a plurality of blocks; calculating a direction field according to the pattern in each of the blocks; calculating a similarity degree between the direction field of a first block and the direction fields of adjacent blocks of the first block; and classifying the first block into a first part according to the similarity degree of the first block.

Abstract: An image processing method includes obtaining a sensed image, wherein the sensed image comprises a pattern; dividing the sensed image into a plurality of blocks; calculating a direction field according to the pattern in each of the blocks; calculating a similarity degree between the direction field of a first block and the direction fields of adjacent blocks of the first block; and classifying the first block into a first part according to the similarity degree of the first block.

Abstract: A touch sensing system includes a touch panel, a driving apparatus and a processing circuit. The touch panel includes a plurality of touch sensing units arranged in form of a matrix. The driving apparatus is configured to drive the touch sensing units, receive a sensing signal from each of the touch sensing units, convert each of the received sensing signals to have a digital format and output the digital sensing signals. The processing circuit is configured to define a matrix of sensing value according to values of the received sensing signals and positions of the respective touch sensing units, scan the non-zero elements in the matrix by a predetermined mean, refer all the located non-zero elements to as a part of the contour of the object and calculating a size of a contour of an object. An operation for the touch sensing system is also provided.

Abstract: A radio frequency identification tag includes a housing shaped as a stripe defining a longitudinal side and an inlay disposed within the housing. The inlay includes a carrier board supporting a packaged chip and a wiring antenna in connection with the packaged chip. The wiring antenna is formed with an electrical joint directly and electrically connecting the packaged chip and an extension portion directly extending out of the electrical joint. The extension direction of the extension portion is substantially perpendicular to the longitudinal side.

Abstract: A chip package of the present invention including a substrate, a chip, at least one electrical connecting element and a solder layer is provided. The substrate has at least one contact. The chip is disposed on the substrate and has at least one pad. The electrical connecting element includes a copper bump and an anti-oxidation layer. The copper bump is disposed on the pad. The anti-oxidation layer is disposed on at least part of an outside surface of the copper bump and the outside surface of the copper bump is not connected to the pad. The solder layer is disposed between the copper bump and the contact. The pad is electrically connected to the contact through the electrical connecting element and solder layer. In addition, a chip element of the present invention is also provided.

Abstract: A radio frequency identification tag comprises a chip; a circuit antenna connected to the chip; and a substrate having a front side carrying the chip and the circuit antenna and formed with a scribing portion, wherein the scribing portion overlaps at least one part of the circuit antenna when viewed from a back side of the substrate.

Abstract: The present disclosure provides a surgical planning and navigation system imports multiple medical imaging sources of the same body part for integrated display in the same coordinate. Images are converted into 3D volumes, spatially co-registering each image volume to a base anatomical image.

Abstract: A touch sensing system includes a touch panel, a driving apparatus and a processing circuit. The touch panel includes a plurality of touch sensing units arranged in form of a matrix. The driving apparatus is configured to drive the touch sensing units, receive a sensing signal from each of the touch sensing units, convert each of the received sensing signals to have a digital format and output the digital sensing signals. The processing circuit is configured to define a matrix of sensing value according to values of the received sensing signals and positions of the respective touch sensing units, scan the non-zero elements in the matrix by a predetermined mean, refer all the located non-zero elements to as a part of the contour of the object and calculating a size of a contour of an object. An operation for the touch sensing system is also provided.

Abstract: A radio frequency identification tag includes a housing shaped as a stripe defining a longitudinal side and an inlay disposed within the housing. The inlay includes a carrier board supporting a packaged chip and a wiring antenna in connection with the packaged chip. The wiring antenna is formed with an electrical joint directly and electrically connecting the packaged chip and an extension portion directly extending out of the electrical joint. The extension direction of the extension portion is substantially perpendicular to the longitudinal side.

Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.

Abstract: A method for delineation of characteristic points in an electrocardiogram signal includes the steps of: (a) processing the electrocardiogram signal to obtain at least one multiscale differential operator wavelet transform thereof; and (b) locating at least one characteristic point in at least one wave segment of the electrocardiogram signal based on the at least one multiscale differential operator wavelet transform.

Abstract: A server and cooler module arrangement includes a server accommodating a stack of an operating system and an electronic device in an accommodation chamber therein at one side and an access device unit in the accommodation chamber at an opposite side, and a cooler module, which comprises a rack mounted in a partition way in the accommodation chamber between the stack of operating system and electronic device and the access device unit and a plurality of fans respectively adjustably mounted in respective open frames at different elevations and adapted for drawing air or sending air toward different heat sources in the operating system, the electronic device and the access device unit for quick dissipation of waste heat.

Abstract: A server and cooler module arrangement includes a server accommodating a stack of an operating system and an electronic device in an accommodation chamber therein at one side and an access device unit in the accommodation chamber at an opposite side, and a cooler module, which comprises a rack mounted in a partition way in the accommodation chamber between the stack of operating system and electronic device and the access device unit and a plurality of fans respectively adjustably mounted in respective open frames at different elevations and adapted for drawing air or sending air toward different heat sources in the operating system, the electronic device and the access device unit for quick dissipation of waste heat.

Abstract: A USB interface provided with USB host/device function and its control method is disclosed. The USB interface includes a control unit, a USB host, a USB device, a memory, a port router and a plurality of connection ports. The control unit is used to define the connection ports to be either an upstream port or downstream port. It also controls signal flows within the USB control interface. The signal flows are provided for the USB host and the USB device. The memory is used to store data during the operation of the USB control interface. The USB host is coupled to an external device via the port router, and the USB device is coupled to an external host via the port router.

Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.

Abstract: An amplifier has a self-bias circuit to generate the bias voltage for the input of the amplifying circuit in the amplifier, thereby simplifying the circuit complexity to reduce the size and cost of the amplifier.