Patents by Inventor Po-Ching Chuang

Po-Ching Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage metal-oxide-semiconductor transistor device and layout pattern thereof
    Patent number: 8937352
    Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang
  • HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF
    Publication number: 20140159155
    Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.
    Type: Application
    Filed: February 17, 2014
    Publication date: June 12, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang
  • High voltage metal-oxide-semiconductor transistor device and layout pattern thereof
    Patent number: 8692326
    Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang
  • HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF
    Publication number: 20130221438
    Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Chih-Wei Hsu, Po-Ching Chuang