Patents by Inventor Po-Ching Hsu
Po-Ching Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8329517Abstract: A method for manufacturing a pixel structure includes providing a substrate including a transistor region and a pixel region, forming at least one gate electrode on the transistor region, forming an insulating layer on the substrate to overlay the gate electrode, and forming a patterned semi-conductive layer on the surface of a portion of the insulating layer disposed on the transistor region and the pixel region. A patterned first protective layer is formed on a portion of the patterned semi-conductive layer corresponding to the gate electrode, and the patterned semi-conductive layer is doped without being overlaid by the patterned first protective layer.Type: GrantFiled: August 31, 2010Date of Patent: December 11, 2012Assignee: Chimei Innolux CorporationInventor: Po-Ching Hsu
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Publication number: 20110068333Abstract: A method for manufacturing a pixel structure includes providing a substrate including a transistor region and a pixel region, forming at least one gate electrode on the transistor region, forming an insulating layer on the substrate to overlay the gate electrode, and forming a patterned semi-conductive layer on the surface of a portion of the insulating layer disposed on the transistor region and the pixel region. A patterned first protective layer is formed on a portion of the patterned semi-conductive layer corresponding to the gate electrode, and the patterned semi-conductive layer is doped without being overlaid by the patterned first protective layer.Type: ApplicationFiled: August 31, 2010Publication date: March 24, 2011Applicant: CHIMEI INNOLUX CORPORATIONInventor: PO-CHING HSU
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Patent number: 7779323Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: August 20, 2008Date of Patent: August 17, 2010Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Publication number: 20090132880Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: August 20, 2008Publication date: May 21, 2009Inventors: Laung-Terng (L.- T.) Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Publication number: 20090037786Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: September 30, 2008Publication date: February 5, 2009Inventors: Laung-Terng Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Patent number: 7444567Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: April 4, 2003Date of Patent: October 28, 2008Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Patent number: 7434126Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: May 30, 2007Date of Patent: October 7, 2008Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
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Publication number: 20070255988Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: May 30, 2007Publication date: November 1, 2007Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
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Patent number: 7284175Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: November 22, 2006Date of Patent: October 16, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Patent number: 7260756Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: April 5, 2005Date of Patent: August 21, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Xiaoqing Wen
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Publication number: 20070168803Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: November 22, 2006Publication date: July 19, 2007Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Patent number: 7191373Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: February 27, 2002Date of Patent: March 13, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu
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Patent number: 7058869Abstract: A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.Type: GrantFiled: January 23, 2004Date of Patent: June 6, 2006Assignee: Syntest Technologies, Inc.Inventors: Khader S. Abdel-Hafez, Xiaoqing Wen, Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Hao-Jan Chao, Hsin-Po Wang
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Patent number: 7007213Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: February 7, 2002Date of Patent: February 28, 2006Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Publication number: 20040268181Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: April 4, 2003Publication date: December 30, 2004Inventors: Laung-Terng Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Publication number: 20040237015Abstract: A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.Type: ApplicationFiled: January 23, 2004Publication date: November 25, 2004Inventors: Khader S. Abdel-Hafez, Xiaoqing Wen, Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Hao-Jan Chao, Hsin-Po Wang
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Publication number: 20020138801Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: February 27, 2002Publication date: September 26, 2002Inventors: Laung-Terng Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu
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Publication number: 20020120896Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: February 7, 2002Publication date: August 29, 2002Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen