Patents by Inventor Po-Chou PAN

Po-Chou PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230074033
    Abstract: An optoelectronic device includes a substrate, a first semiconductor stack located on the substrate, a second semiconductor stack located on the first semiconductor stack, and a first optical structure located between the first semiconductor stack and the second semiconductor stack. The first semiconductor stack includes a first semiconductor layer, a second semiconductor layer and a first active layer which emits or absorbs a first light with a first wavelength. The second semiconductor stack includes a third semiconductor layer, a fourth semiconductor layer and a second active layer which emits or absorbs a second light with a second wavelength smaller than the first wavelength. The first optical structure includes a plurality of first parts and a plurality of second parts. The first parts and the second parts are alternately arranged by a first period along a horizontal direction parallel to the substrate.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 9, 2023
    Inventors: Wei-Jen Hsueh, Shih-Chang Lee, Chen Ou, Po-Chou Pan, Wen-Luh Liao
  • Publication number: 20230027930
    Abstract: A semiconductor device is provided, which includes a substrate, a first semiconductor structure, a plurality of first holes, a first dielectric structure and a second semiconductor structure. The first semiconductor structure is located on the substrate. The first holes are periodically arranged in the first semiconductor structure. The first dielectric structure is filled in one or more of the first holes. The second semiconductor structure is located on the first semiconductor structure.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 26, 2023
    Inventors: Po-Chou Pan, Shih-Chang Lee, Wei-Jen Hsueh, Sheng-Feng Kuo
  • Patent number: 11094609
    Abstract: A thermal dissipation structure for integrated circuits includes a semiconductor substrate, a thermal dissipation trench, a metal seed layer and a metal layer. The semiconductor substrate has a first surface and a second surface which is opposite to the first surface. Integrated circuits are located on and thermally coupled with the first surface. The thermal dissipation trench is formed within the second surface. The metal seed layer seals the thermal dissipation trench to define a thermal dissipation channel. The thermal dissipation channel includes an inlet and an outlet. The metal layer is an electroplated layer formed from the metal seed layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ray-Hua Horng, Po-Chou Pan
  • Publication number: 20210013127
    Abstract: A thermal dissipation structure for integrated circuits includes a semiconductor substrate, a thermal dissipation trench, a metal seed layer and a metal layer. The semiconductor substrate has a first surface and a second surface which is opposite to the first surface. Integrated circuits are located on and thermally coupled with the first surface. The thermal dissipation trench is formed within the second surface. The metal seed layer seals the thermal dissipation trench to define a thermal dissipation channel. The thermal dissipation channel includes an inlet and an outlet. The metal layer is an electroplated layer formed from the metal seed layer.
    Type: Application
    Filed: March 20, 2020
    Publication date: January 14, 2021
    Inventors: Ray-Hua HORNG, Po-Chou PAN