Abstract: A zoned heat dissipation control system for a water cooling radiator and a water cooling heat dissipation system having the zoned heat dissipation control system includes a plurality of fans, a plurality of heat dissipation zones defined on the water cooling radiator, a thermal detector, and a control unit. At least one of the fans is disposed within each of the heat dissipation zones. The thermal detector is disposed within at least one of the heat dissipation zones and configured to detect the temperature of the water cooling radiator. The control unit is electrically connected to the fans and the thermal detector and configured to modulate the rotational speed of the fan within each of the heat dissipation zones based on the detected data from the thermal detector.

Abstract: An interactive information system includes: a first frame, a first interactive module arranged in the first frame, a second frame, a control module arranged in the second frame and configured to generate a graphic user interface (GUI) and to perform a function of the interactive information system based on the first user input; and a first internal cable connecting the first interactive module bridge board and the control module and configured to transmit the plurality of inter-frame signals between the first frame and the second frame. The first interactive module includes: a first display module for display of the GUI; a first touch input module configured to receive a first user input to the GUI; and a first interactive module bridge board configured to transmit a plurality of inter-frame signals comprising electrical signals of the first display module and the first touch input module.

Abstract: A semiconductor structure includes a combined feature, a protection layer and a polymeric layer. The combined feature includes a passivation layer, an interconnecting structure disposed on the passivation layer, and a dielectric layer disposed on the passivation layer and the interconnecting structure. The protection layer is disposed on the dielectric layer, and is oxide-and-nitride based. The polymeric layer is disposed on the protection layer, and is separated from the interconnecting structure by the protection layer. A method of making a semiconductor structure is also provided.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: The invention provides a voltage doubler switched capacitor circuit capable of detecting short circuit of flying capacitor and a detection method thereof. The voltage doubler switched capacitor circuit provides a way to connect the flying capacitor in parallel to the charging path, and calculate whether it is charged to a predetermined voltage in the designed charging time interval, and then it can effectively detect whether the flying capacitor is short-circuited.

Abstract: A first communication device capable of selecting a bandwidth, includes a receiving module, for receiving a wireless signal from a second communication device according to a first bandwidth; a measurement module, coupled to the receiving module, for measuring a communication quality of the wireless signal; and a processing module, coupled to the measurement module, for selecting a second bandwidth according to the first bandwidth and the communication quality; and a transmission module, coupled to the processing module, for transmitting information of the second bandwidth to the second communication device, for the second communication device to transmit the wireless signal to the fist communication device according to the second bandwidth.

Abstract: The invention provides a voltage doubler switched capacitor circuit capable of detecting short circuit of flying capacitor and a detection method thereof. The voltage doubler switched capacitor circuit provides a way to connect the flying capacitor in parallel to the charging path, and calculate whether it is charged to a predetermined voltage in the designed charging time interval, and then it can effectively detect whether the flying capacitor is short-circuited.

Abstract: Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on a side of a chip bonding area of a package carrier thereof. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on at a side of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and adjacent first bonding pads on the side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Abstract: Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on a side of a chip bonding area of a package carrier thereof. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on at a side of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and adjacent first bonding pads on the side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Abstract: An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.

Abstract: An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

Abstract: A circuit switch comprises a first circuit board, a second circuit board and a third circuit board which are intact and sequentially parallel to each other; and a dual ramp means, wherein a first end of the first circuit board and a first end of the third circuit board contacts with the two ramps of the dual ramp means, respectively, a first end of the second circuit board does not contact with the dual ramp means, the first end of the second circuit board comprises a circuit, a second point and a third point of the circuit contacts with and electrically couples to a first point of the first circuit board and a fourth point of the third circuit board, respectively.

Abstract: A multichannel touch controller includes a signal receiving circuit having N electrode pins electrically connected to touch screen for receiving respective sensing signals, switching circuit having N switch sets each consisting of first switch and second switch respectively connected in parallel to the N electrode pins, microcontroller, and processing unit having N analog front-end circuits and analog-to-digital converters with N analog front-end circuits respectively electrically connected to the first switches, the 2nd analog front-end circuit and the N+1 analog front-end circuits respectively electrically connected to the second switches and the analog-to-digital converters respectively electrically connecting the analog front-end circuits to the microcontroller (MCU) to constitute N+1 channels for processing sensing signals so that when one channel fails, the microcontroller switches off the respective first switch and switches on the respective second switch so as to skip the failed channel until switchi

Abstract: An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.

Abstract: An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

Abstract: The present invention provides a recording method of touch information timing. The method comprises receiving a first touch point information, determining whether the first touch point is the beginning point of a trace; and recording a first timing with respect to the receiving of the first touch point information if the first touch point is the beginning point of the trace.