Patents by Inventor Po-Chun Fan
Po-Chun Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130246Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
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Patent number: 11957061Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: 11925035Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.Type: GrantFiled: October 26, 2022Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Patent number: 11175920Abstract: A computing device operative to perform parallel computations. The computing device includes a controller unit to assign workgroups to a set of batches. Each batch includes a program counter shared by M workgroups assigned to the batch, where M is a positive integer determined according to a configurable batch setting. Each batch further includes a set of thread processing units operative to execute, in parallel, a subset of work items in each of the M workgroups. Each batch further includes a spilling memory to store intermediate data of the M workgroups when one or more workgroups in the M workgroups encounters a synchronization barrier.Type: GrantFiled: April 25, 2019Date of Patent: November 16, 2021Assignee: MediaTek Inc.Inventors: Shou-Jen Lai, Pei-Kuei Tsung, Po-Chun Fan, Sung-Fang Tsai
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Patent number: 10838656Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.Type: GrantFiled: August 12, 2017Date of Patent: November 17, 2020Assignee: MediaTek Inc.Inventors: Po-Chun Fan, Pei-Kuei Tsung, Sung-Fang Tsai, Chia-Hsien Chou, Shou-Jen Lai
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Patent number: 10394929Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.Type: GrantFiled: October 19, 2017Date of Patent: August 27, 2019Assignee: MediaTek, Inc.Inventors: Sung-Fang Tsai, Pei-Kuei Tsung, Po-Chun Fan, Shou-Jen Lai
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Publication number: 20190250924Abstract: A computing device operative to perform parallel computations. The computing device includes a controller unit to assign workgroups to a set of batches. Each batch includes a program counter shared by M workgroups assigned to the batch, where M is a positive integer determined according to a configurable batch setting. Each batch further includes a set of thread processing units operative to execute, in parallel, a subset of work items in each of the M workgroups. Each batch further includes a spilling memory to store intermediate data of the M workgroups when one or more workgroups in the M workgroups encounters a synchronization barrier.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Shou-Jen Lai, Pei-Kuei Tsung, Po-Chun Fan, Sung-Fang Tsai
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Patent number: 10324730Abstract: A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.Type: GrantFiled: October 4, 2016Date of Patent: June 18, 2019Assignee: MediaTek, Inc.Inventors: Shou-Jen Lai, Pei-Kuei Tsung, Po-Chun Fan, Sung-Fang Tsai
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Publication number: 20180173676Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.Type: ApplicationFiled: October 19, 2017Publication date: June 21, 2018Inventors: Sung-Fang Tsai, Pei-Kuei Tsung, Po-Chun Fan, Shou-Jen Lai
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Publication number: 20180173463Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.Type: ApplicationFiled: August 12, 2017Publication date: June 21, 2018Inventors: Po-Chun Fan, Pei-Kuei Tsung, Sung-Fang Tsai, Chia-Hsien Chou, Shou-Jen Lai
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Publication number: 20170277567Abstract: A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.Type: ApplicationFiled: October 4, 2016Publication date: September 28, 2017Inventors: Shou-Jen Lai, Pei-Kuei Tsung, Po-Chun Fan, Sung-Fang Tsai
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Patent number: 9760969Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.Type: GrantFiled: March 9, 2015Date of Patent: September 12, 2017Assignee: MEDIATEK INC.Inventors: Ming-Hao Liao, Shou-Jen Lai, Chia-Hsien Chou, Po-Chun Fan, Yan-Hong Lu, Chih-Chung Cheng, Hung-Yau Lin
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Patent number: 9507601Abstract: An apparatus for processing a plurality of data sets is disclosed, wherein one data set of the plurality of data sets includes N components and has a data type of one of a scalar type and a vector type, wherein N is a positive integer number. The apparatus includes a memory module and a data accessing module. The memory module comprises N memory units configured to store the plurality of data sets. The data accessing module is configured to write the data set into the memory module according to a write data index corresponding to the data set and one of a first writing mapping information and a second writing mapping information, wherein the first writing mapping information is employed when the data type is one of the scalar and the vector type and the second writing mapping information is employed when the data type is the other of the scalar and the vector type.Type: GrantFiled: February 19, 2014Date of Patent: November 29, 2016Assignee: MEDIATEK INC.Inventors: Pei-Kuei Tsung, Mu-Fan Murphy Chang, Po-Chun Fan
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Publication number: 20160267621Abstract: A graphic processing system and a method of graphic processing are provided. The graphic processing system has a collector, a plurality of slots, a scheduler, an arbiter and at least an arithmetic logic unit (ALU). The collector is configured to group a plurality of workitems into elementary wavefronts. Each of the elementary wavefronts comprises workitems configured to execute the same kernel code. The scheduler is configured to allocate the elementary wavefronts to the slots. Two or more of the elementary wavefronts exist at one slot to form one of a plurality of macro wavefronts. The arbiter is configured to select one of the macro wavefronts. The ALU is configured to execute workitems of at least an elementary wavefront of the selected macro wavefront and output results of execution of the workitems.Type: ApplicationFiled: March 9, 2015Publication date: September 15, 2016Inventors: Ming-Hao Liao, Shou-Jen Lai, Chia-Hsien Chou, Po-Chun Fan, Yan-Hong Lu, Chih-Chung Cheng, Hung-Yau Lin
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Publication number: 20150234662Abstract: An apparatus for processing a plurality of data sets is disclosed, wherein one data set of the plurality of data sets includes N components and has a data type of one of a scalar type and a vector type, wherein N is a positive integer number. The apparatus includes a memory module and a data accessing module. The memory module comprises N memory units configured to store the plurality of data sets. The data accessing module is configured to write the data set into the memory module according to a write data index corresponding to the data set and one of a first writing mapping information and a second writing mapping information, wherein the first writing mapping information is employed when the data type is one of the scalar and the vector type and the second writing mapping information is employed when the data type is the other of the scalar and the vector type.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: MEDIATEK INC.Inventors: Pei-Kuei Tsung, Mu-Fan Murphy Chang, Po-Chun Fan