Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A computer implemented method for managing the scope of permissions granted by users to application that includes collecting a set of permissions for an application from an application provider publication; and collecting a process flow for functional steps of the application from a review of the application that is published on a product review type publication. The computer implemented method further includes dividing the functional steps of the application into a plurality of journeys, each of said plurality of journeys having a function associated with a stage of a functional step from a perspective of a user; and matching permissions from the set of permissions for each journey of said plurality of journeys to provide matched permissible permissions to journeys stored in a customer journey store.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: An electronic device is adapted to be electrically connected with an input device and at least one display unit. The electronic device includes a processor configured to convert an input instruction from the input device to a corresponding a control instruction and transmit the control instruction to the display unit. The display unit displays the OSD menu or executes the adjustment function of the OSD menu according to the control instruction.

Abstract: A memory storage device having a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit and a memory control circuit unit is provided. When an external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device via the second connection interface unit, supplies an operation voltage to the rewritable non-volatile memory module and the memory control circuit unit and supplies the second power supply voltage to a host device. When the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a first power supply voltage from the host device via the first connection interface unit and supplies the operation voltage to the memory control circuit unit and the rewritable non-volatile memory module.

Abstract: A memory storage device having a rewritable non-volatile memory module, a first connection interface unit, a second connection interface unit, a power management circuit and a memory control circuit unit is provided. When an external power supply device is electrically connected to the second connection interface unit, the power management circuit receives a second power supply voltage from the external power supply device via the second connection interface unit, supplies an operation voltage to the rewritable non-volatile memory module and the memory control circuit unit and supplies the second power supply voltage to a host device. When the external power supply device is electrically disconnected with the second connection interface unit, the power management circuit receives a first power supply voltage from the host device via the first connection interface unit and supplies the operation voltage to the memory control circuit unit and the rewritable non-volatile memory module.

Abstract: The embodiments of the present disclosure provide an AMOLED panel and method of encapsulating the same. The AMOLED panel comprises: a substrate; a plurality of TFTs arranged on the substrate spaced from each other; a cover, at a surface towards the substrate, the cover is provided with recesses corresponding to the plurality of TFTs and spacing parts formed between recesses; the cover covers on the substrate and TFTs; each TFT is received in each recess correspondingly, and the spacing parts are positioned between neighboring TFTs respectively; and a sealing layer connecting the spacing parts to the substrate. The present disclosure facilitates to control the flatness of the AMOLED panel.

Abstract: ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.

Abstract: ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting.

Abstract: A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

Abstract: A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.