Patents by Inventor Po-Chung Huang

Po-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984314
    Abstract: A particle removal method for removing particles on the backside of a reticle is provided. The method includes disposing the reticle on a reticle holder. In addition, the method includes moving a baffle defining an enclosed area that encompasses a particle to be removed on a backside of the reticle. The method further includes spraying, by a solution spraying module of a particle removal device, a solution onto the particle. The method further includes sucking, by a sucking module of the particle removal device, the solution on the reticle with the particle. The method further includes emitting, by the particle removal device, a gas onto the backside of the reticle for drying the backside.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Siao-Chian Huang, Po-Chung Cheng, Ching-Juinn Huang, Tzung-Chi Fu, Tsung-Yen Lee
  • Patent number: 11983475
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20240071865
    Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Inventors: Xinyu Bao, Lee-Chung Lu, Jyh Chwen Frank Lee, Fong-Yuan Chang, Sam Vaziri, Po-Hsiang Huang
  • Patent number: 8722450
    Abstract: The present invention generally relates to a method for manufacturing an improved solar cell module, more particularly to a method for manufacturing the improved solar cell module that may not happen problems of power leakage and short circuit and save the cost to manufacturing.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Perfect Source Technology Corp.
    Inventor: Po-Chung Huang