Patents by Inventor Po-Han CHENG

Po-Han CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic device and performance optimization method thereof
    Patent number: 12093111
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: September 17, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
  • ELECTRONIC DEVICE AND PERFORMANCE OPTIMIZATION METHOD THEREOF
    Publication number: 20240272696
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor and a controller. The battery module is configured to supply power to the electronic device. The processor has a power consumption limit. In a power connection state, the controller determines whether to disable a power consumption limit adjustment function of the processor according to a source power provided by a power adapter and a system performance use setting of the electronic device. When the power consumption limit adjustment function is disabled, the processor executes an application program to monitor a storage capacity of the battery module and adjusts the system performance usage setting according to the storage capacity.
    Type: Application
    Filed: November 14, 2023
    Publication date: August 15, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Kuo Ko, Po-Han Cheng, Po-Hsin Chang, Huei-Ling Lai
  • ELECTRONIC DEVICE AND PERFORMANCE OPTIMIZATION METHOD THEREOF
    Publication number: 20230266813
    Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.
    Type: Application
    Filed: October 14, 2022
    Publication date: August 24, 2023
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Po-Han Cheng, Chin-Chang Chang, Po-Hsin Chang, Shih-Hao Chen, Kai-Peng Chung, Ci-Syuan Wu, Chun Tsao, Teng-Chih Wang, Sheng-Yi Chen, Guan-Heng Lai
  • Magnetoresistive element and magnetic memory device
    Patent number: 10305027
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 28, 2019
    Assignees: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi Kato, Tadaomi Daibou, Yuuzo Kamiguchi, Naoharu Shimomura, Junichi Ito, Hiroaki Sukegawa, Mohamed Belmoubarik, Po-Han Cheng, Seiji Mitani, Tadakatsu Ohkubo, Kazuhiro Hono
  • MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY DEVICE
    Publication number: 20180090671
    Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first nonmagnetic layer includes an oxide including an inverse-spinel structure.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 29, 2018
    Applicants: Kabushiki Kaisha Toshiba, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yushi KATO, Tadaomi DAIBOU, Yuuzo KAMIGUCHI, Naoharu SHIMOMURA, Junichi ITO, Hiroaki SUKEGAWA, Mohamed BELMOUBARIK, Po-Han CHENG, Seiji MITANI, Tadakatsu OHKUBO, Kazuhiro HONO