Abstract: A nano-twinned structure on a metallic thin film surface is provided. The nano-twinned structure includes a substrate, an adhesive-lattice-buffer layer over the substrate, and a metallic thin film including Ag, Cu, Au, Pd or Ni over the adhesive-lattice-buffer layer. The bottom region of the metallic thin film has equi-axial coarse grains. The surface region of the metallic thin film contains parallel-arranged high-density twin boundaries (?3+?9) with a pitch from 1 nm to 100 nm. The quantity of the parallel-arranged twin boundaries is 50% to 80% of the total quantity of twin boundaries in the cross-sectional view of the metallic thin film. The parallel-arranged twin boundaries include 30% to 90% [111] crystal orientation. The nano-twinned structure on the metallic thin film surface is formed through a post-deposition ion bombardment on the evaporated metallic thin film surface after the evaporation process.

Abstract: A school admission prediction system and method are provided. The system includes a user interface for receiving personal data from an applicant, including academic and activity data. A data acquisition module connected to the user interface acquires this personal data. A data preprocessing module connected to the data acquisition module preprocesses the academic and activity data. An attribute selection module connected to the data preprocessing module extracts multiple attributes from the preprocessed data. A machine learning model generates an evaluation report based on the extracted attributes. This report includes a prediction of whether the applicant will be admitted to the school. The system also includes a loss calculation module for evaluating the performance of the machine learning model and optimizing its parameters based on the evaluation results. The method and system provide a reliable and efficient way to predict school admissions, helping applicants to better prepare their applications.

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

Abstract: A semiconductor structure includes a base structure, a first portion, a second portion and a first stack. The first portion and the second portion are disposed on the base structure and are respectively made of a first semiconductor material and a second semiconductor material which has a conductivity type opposite to that of the first semiconductor material. The first stack is disposed on the base structure and between the first portion and the second portion. The first stack includes a plurality of first semiconductor regions and a plurality of first dielectric regions disposed to alternate with the first semiconductor regions, such that each of the first semiconductor regions and the first dielectric regions extends between the first portion and the second portion. The first semiconductor regions has a dopant concentration which is lower than that of each of the first portion and the second portion.

Abstract: A semiconductor structure includes a base structure, at least one diode device and a semiconductor device. The base structure has a first base region and a second base region. The at least one diode device includes a first feature formed in the first base region, and a second feature formed over the first feature and having a conductivity type opposite to that of the first feature. The semiconductor device is formed on the second base region.

Abstract: A semiconductor structure includes a first transistor and a second transistor. The first transistor includes a first fin structure and a first metal gate over the first fin structure. The first metal gate includes a first work function metal layer and a first gap-filling metal layer. The second transistor includes a second fin structure and a second metal gate over the second fin structure. The second metal gate includes a second work function metal layer and a second gap-filling metal layer. The first metal gate and the second metal gate provide a same work function. A width of the first metal gate is equal to a width of the second metal gate. A width of a top surface of the first gap-filling metal layer is greater than a width of a top surface of the second gap-filling metal layer.

Abstract: Embodiments include a method for forming an integrated circuit package. A first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. A first metallization pattern is formed extending along and through the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. The second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. After the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. The wafer and the first dielectric layer are sawed in the scribe line region.

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The device includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.

Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.

Abstract: An optical structure is provided. The optical structure includes a substrate and multiple films disposed on the substrate. The multiple films include a first set of multiple films and a second set of multiple films. The first set of multiple films includes a plurality of first material layers and a plurality of second material layers including germanium oxide, germanium nitride or germanium hydroxide which are arranged in an alternating manner. The second set of multiple films includes a plurality of third material layers including germanium oxide, germanium nitride or germanium hydroxide and a plurality of fourth material layers which are arranged in an alternating manner. The thickness of the fourth material layer is greater than that of the first material layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a first trench over a first portion of the substrate and a second trench over a second portion of the substrate. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

Abstract: A data processing device includes a base plate and an electronic module. The base plate includes N driving portions. The electronic module includes an electronic component, a tray and a recognition mechanism. The tray is configured to support the electronic component and includes N slots. The tray is disposed on the base plate, such that an i-th driving portion of the N driving portions is disposed in an i-th slot of the N slots. The recognition mechanism is disposed on the tray. The recognition mechanism includes N interfering portions and N receiving recesses. When the tray moves with respect to the base plate toward a first direction, the i-th driving portion moves within the i-th slot toward a second direction to push an i-th interfering portion of the N interfering portions to move, such that the i-th interfering portion extends into an i-th receiving recess of the N receiving recesses.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A device with lock function includes a housing, a casing and a lock mechanism. The housing has a first engaging portion. The lock mechanism includes a frame, a lock member, a first elastic member, an operating member and an unlock member. The frame has a second engaging portion. The lock member has a third engaging portion engaging with the first engaging portion to lock the casing in the housing. The unlock member has a fourth engaging portion engaging with the second engaging portion to restrain the operating member. When the unlock member is pressed, the fourth engaging portion disengages from the second engaging portion and the first elastic member drives the lock member to move toward an inside of the frame, such that the third engaging portion disengages from the first engaging portion and the lock member drives the operating member to move toward an outside of the frame.

Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.

Abstract: A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.