Patents by Inventor Po-Hao Chang

Po-Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961762
    Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
  • Publication number: 20240121523
    Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Kai-Hao CHANG, Chun-Yuan WANG, Shin-Hong KUO, Zong-Ru TU, Po-Hsiang WANG, Chih-Ming WANG
  • Publication number: 20240114458
    Abstract: The present invention provides a wireless communication method, wherein the wireless communication method includes the steps of: controlling the electronic device to operate in an active mode and communicating with an access point; after a traffic between the electronic device and the access point ends, controlling the electronic device to operate in a first mode, and transmitting a null frame to notify the access point that the electronic device enters a power saving mode; and during the first mode, controlling the electronic device to leave the power saving mode and transmitting at least one query signal to the access point to ask data.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Applicant: MEDIATEK INC.
    Inventors: Cheng-Kung Lai, Chia-Ning Chang, Po-Hao Hsiao
  • Publication number: 20240096917
    Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: PO CHUN CHANG, PING-HAO LIN, WEI-LIN CHEN, KUN-HUI LIN, KUO-CHENG LEE
  • Patent number: 11922044
    Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 5, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Yu-Hao Chang, Yu-Han Hsiao, Po-Sheng Chou
  • Publication number: 20230317708
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 5, 2023
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Patent number: 11646302
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 9, 2023
    Assignee: Apple Inc.
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Patent number: 11458208
    Abstract: The invention relates to antibody fusion proteins. Particularly, the invention relates to antibody fusion proteins for intra-cellular and intra-nucleus drugs delivery. The fusion protein of the invention can be used as a peptide penetration system that specifically binds to various targets for the delivery of effector peptides across a biological barrier.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 4, 2022
    Assignee: ASCLEPIUMM TAIWAN CO., LTD
    Inventors: Min-che Chen, Ya-chuan Liu, Po-hao Chang, Ya-ping Tsai, Chun-wei Chen, Pei-yi Lee
  • Publication number: 20220238446
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: MediaTek Inc.
    Inventors: Po-Hao CHANG, Yi-Jou Lin, Hung-Chuan Chen
  • Patent number: 11342267
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Po-Hao Chang, Yi-Jou Lin, Hung-Chuan Chen
  • Publication number: 20210305227
    Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 30, 2021
    Inventors: Wei Chen, Jie-Hua Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke, Kunzhong Hu
  • Patent number: 10836823
    Abstract: The invention provides antibodies against the antigen containing the Dsg2 extracellular domain 2. Also provided is the method of using the antibodies in treatment or prevention of a cancer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 17, 2020
    Assignee: ASCLEPIUMM TAIWAN CO., LTD.
    Inventors: Min-che Chen, Po-hao Chang, Ya-chuan Liu
  • Publication number: 20200168548
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 28, 2020
    Inventors: Po-Hao CHANG, Yi-Jou LIN, Hung-Chuan CHEN
  • Publication number: 20190298848
    Abstract: The invention relates to antibody fusion proteins. Particularly, the invention relates to antibody fusion proteins for intra-cellular and intra-nucleus drugs delivery. The fusion protein of the invention can be used as a peptide penetration system that specifically binds to various targets for the delivery of effector peptides across a biological barrier.
    Type: Application
    Filed: June 6, 2017
    Publication date: October 3, 2019
    Inventors: Min-che CHEN, Ya-chuan LIU, Po-hao CHANG, Ya-ping TSAI, Chun-wei CHEN, Pei-yi LEE
  • Publication number: 20190300604
    Abstract: The invention provides antibodies against the antigen containing the Dsg2 extracellular domain 2. Also provided is the method of using the antibodies in treatment or prevention of a cancer.
    Type: Application
    Filed: June 6, 2016
    Publication date: October 3, 2019
    Applicant: Asclepiumm Taiwan Co., Ltd
    Inventors: Min-che CHEN, Po-hao CHANG, Ya-chuan LIU
  • Publication number: 20160218092
    Abstract: A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.
    Type: Application
    Filed: October 23, 2015
    Publication date: July 28, 2016
    Inventors: Po-Hao Chang, Chun-Wei Chang, Ching-Chih Li