Patents by Inventor Po-Hao Huang
Po-Hao Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12183629Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: GrantFiled: July 20, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
-
Patent number: 12159791Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.Type: GrantFiled: July 24, 2023Date of Patent: December 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
-
Publication number: 20240387257Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
-
Publication number: 20240387274Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Szu-Chi Yang, Allen Chien, Tsai-Yu Huang, Chien-Chih Lin, Po-Kai Hsiao, Shih-Hao Lin, Chien-Chih Lee, Chih Chieh Yeh, Cheng-Ting Ding, Tsung-Hung Lee
-
Publication number: 20240379380Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Sheng-Chun YANG, Po-Chih HUANG, Chih-Lung CHENG, Yi-Ming LIN, Chen-Hao LIAO, Min-Cheng CHUNG
-
Publication number: 20240371839Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Fong-Yuan Chang, Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen, Keh-Jeng Chang
-
Publication number: 20240371840Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
-
Publication number: 20240365677Abstract: Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.Type: ApplicationFiled: June 6, 2023Publication date: October 31, 2024Applicant: United Microelectronics Corp.Inventors: Jia-Rong Wu, Yi-An Shih, Hsiu-Hao Hu, I-Fan Chang, Rai-Min Huang, Po Kai Hsu
-
Patent number: 12118315Abstract: Event intensity assessment can include detecting an event description within textual input received via a data communication network. An event-correlated data structure based on the event can be generated, the event-correlated data structure including an event descriptor corresponding to the event. An event sentiment can be determined based on the event descriptor and an event impact based on a quantitative temporal-spatial measure corresponding to the event. An event intensity can be determined based on the event sentiment and event impact. A GUI can be modified in response to the event intensity exceeding a predetermined threshold. The GUI can be modified to indicate the event and the event intensity.Type: GrantFiled: December 28, 2021Date of Patent: October 15, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Biplav Srivastava, Javid Huseynov, Anushree B. Mehta, Po-Hao Huang
-
Publication number: 20240324888Abstract: A sport assistance system and a sport assistance method are provided. The sport assistance method includes: obtaining a real-time heart rate; executing a first assistance procedure according to a target heart rate, a maximum heart rate, a resting heart rate, a first media and the real-time heart rate; and executing a second assistance procedure according to the target heart rate and the real-time heart rate. The first assistance procedure includes: playing the first media at a first tempo rate; and adjusting the first tempo rate according to the real-time heart rate until the real-time heart rate is close to the target heart rate and a first scheduled time is met. The first initial value is greater than the resting heart rate. The second assistance procedure includes: playing a second media; and adjusting a second tempo rate according to an adjustment parameter until a second scheduled time is met.Type: ApplicationFiled: March 29, 2024Publication date: October 3, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ming-Chieh TSAI, Ching-Yu HUANG, Ying-Han HUANG, Yoong-Kee SEK, Po-Ta CHUANG, Yan-Hao HUANG
-
Publication number: 20240321780Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.Type: ApplicationFiled: June 4, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
-
Patent number: 12087745Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.Type: GrantFiled: October 26, 2023Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
-
Patent number: 12083679Abstract: A stabilization method incorporated with a mobile robot having a body, a plane-pressure sensor, and a movement mechanism is disclosed and includes the following steps: sensing and obtaining a pressure distribution of the body through the plane-pressure sensor; computing a center of gravity (CoG) position of the body in accordance with the pressure distribution; determining whether the CoG position is located within a steady zone pre-defined upon the body; and, providing a reverse force toward a CoG offset direction of the CoG position when the CoG position is determined to be off the steady zone.Type: GrantFiled: August 4, 2022Date of Patent: September 10, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Cheng-Hao Huang, Po-Chiao Huang, Han-Ching Lin, Shi-Yu Wang
-
Patent number: 12074148Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.Type: GrantFiled: December 2, 2022Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen, Keh-Jeng Chang
-
Publication number: 20230206001Abstract: Event intensity assessment can include detecting an event description within textual input received via a data communication network. An event-correlated data structure based on the event can be generated, the event-correlated data structure including an event descriptor corresponding to the event. An event sentiment can be determined based on the event descriptor and an event impact based on a quantitative temporal-spatial measure corresponding to the event. An event intensity can be determined based on the event sentiment and event impact. A GUI can be modified in response to the event intensity exceeding a predetermined threshold. The GUI can be modified to indicate the event and the event intensity.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Biplav Srivastava, Javid Huseynov, Anushree B. Mehta, Po-Hao Huang
-
Patent number: 11076755Abstract: An endoscope particularly suited for endocranial procedures and a method of using the endoscope. In some examples the endoscope is rigid except for a bend/tilt portion near a distal end of a rigid tube that is inserted in a patient's cranium, which distal end is controlled in a degree and direction of tilt with a finger operated controller at the endoscope's handle. Some examples use telescoping tubes that allow customizing the endoscope size for specific procedures. A distal portion of the endoscope can be disposable, supplied in a sterile package for a single procedure, thus taking into account contamination dangers that are particularly high for intracranial and certain other interventions and the fact that it can be difficult or impossible to effectively autoclave heat-sensitive components of certain endoscopes or effectively sterilize them using other techniques.Type: GrantFiled: March 26, 2019Date of Patent: August 3, 2021Assignee: Clearmind Biomedical, Inc.Inventors: Po-Hao Huang, Feng-Cheng Chang, Sheng-Chi Lin
-
Patent number: 10915464Abstract: A security system includes a physical unclonable function circuit, a write-in protection circuit, a memory, and a readout decryption circuit. The physical unclonable function circuit provides a plurality of random bit strings. The write-in protection circuit receives a write-in address and original data, and includes an address scrambling unit. The address scrambling unit generates a scrambled address by scrambling a write-in address according to a random bit string provided by the physical unclonable function circuit. The memory stores the storage data corresponding to the original data according to the scrambled address. The readout decryption circuit reads out the storage data from the memory according to the write-in address to derive the original data.Type: GrantFiled: September 10, 2018Date of Patent: February 9, 2021Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Meng-Yi Wu, Po-Hao Huang
-
Patent number: D1000456Type: GrantFiled: July 13, 2021Date of Patent: October 3, 2023Assignee: AI BIOELECTRONIC HEALTHTECH CO. LTD.Inventors: Yen-Yi Ho, Huei-Yun Gong, Yen-Yun Huang, Po-Hao Huang
-
Patent number: D1001140Type: GrantFiled: July 13, 2021Date of Patent: October 10, 2023Assignee: AI BIOELECTRONIC HEALTHTECH CO. LTD.Inventors: Yen-Yi Ho, Huei-Yun Gong, Yen-Yun Huang, Po-Hao Huang
-
Patent number: D1023047Type: GrantFiled: September 14, 2023Date of Patent: April 16, 2024Assignee: AI BIOLECTRONIC HEALTHTECH CO. LIMITEDInventors: Yen-Yi Ho, Huei-Yun Gong, Yen-Yun Huang, Po-Hao Huang