Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.

Abstract: A dynamic scaling processor device and processing method thereof, having a timing decoder, a multi-cycle controller, a correction flip-flop. The timing decoder is provided with a plurality of cycles therein, to receive a plurality of instructions, to select corresponding cycles as its predetermined cycles based on type of each instruction, and output the predetermined cycles and its corresponding instructions to the multi-cycle controller. The multi-cycle controller computes results of the instructions based on the predetermined cycles or a single cycle, and outputs them to the correction flip-flop. The error detection flip-flop utilizes a first clock signal and a stalled second clock signal, to sample a same result, and correct the results when outcomes of samplings are different.