Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A fastener is adapted for assembling a first housing to a second housing. The first housing is provided with a protruding portion and a buckling portion, and the second housing has a first surface, a second surface, and a through hole. The fastener includes a first portion, at least one connecting portion, at least two elastic portions, and a second portion. The first portion movably abuts against the first surface and has a first opening. The connecting portion is accommodated in the through hole. One end of the connecting portion is connected to the first portion. The connecting portion is spaced apart from an inner edge of the second housing by a gap. The two elastic portions inclinedly extend into the first opening. The second portion movably abuts against the second surface and is disposed at the another end of the connecting portion.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: An apparatus for producing silicon carbide crystal is provided and includes a composite structure formed by a plurality of graphite layers and silicon carbide seed crystals, wherein a density or thickness of each layer of graphite is gradually adjusted to reduce a difference of a thermal expansion coefficient and Young's modulus between the graphite layers and silicon carbide. The composite structure can be stabilized on a top portion or an upper cover of a crucible made of graphite, thereby preventing the silicon carbide crystal from falling off.

Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: An active pixel sensor device and the method thereof include an active pixel sensing array and a synchronous reading circuit. The active pixel sensing array is formed by a plurality of sensing pixels disposed in a form of an array. Each sensing pixel has a power terminal. The synchronous reading circuit connects to the power terminals of all sensing pixels, detects a summation of currents flowing through all sensing pixels, converts the summation of currents to an output signal, and outputs the output signal that represents the optical sensing information. In addition to reading each sensing pixel, the active pixel sensor device further controls the synchronous reading circuit to read the output signal corresponding to the summation of currents of all sensing pixels. The active pixel sensor device using the same active pixel sensing array can be applied to large-area sensing.

Abstract: A pixel sensor device has a first sensing unit, a second sensing unit, a first control and reading unit, and a second control and reading unit. The first and second sensing units are disposed concentrically. The first and second control and reading units are connected respectively to the first and second sensing units for separately or simultaneously controlling the first and second sensing units to perform sensing. Since the first and second sensing units are formed by a single pixel sensing array and arranged concentrically, only a single focusing element is required to align centers of the first and second sensing units during the manufacturing process. This achieves high focus accuracy and increases precision in recognition. In the applications of fingerprint recognition and pulse measurement, the user only uses a single finger for sensing so that inaccurate focusing resulted from moving finger is avoided.

Abstract: An active pixel sensor device and the method thereof include an active pixel sensing array and a synchronous reading circuit. The active pixel sensing array is formed by a plurality of sensing pixels disposed in a form of an array. Each sensing pixel has a power terminal. The synchronous reading circuit connects to the power terminals of all sensing pixels, detects a summation of currents flowing through all sensing pixels, converts the summation of currents to an output signal, and outputs the output signal that represents the optical sensing information. In addition to reading each sensing pixel, the active pixel sensor device further controls the synchronous reading circuit to read the output signal corresponding to the summation of currents of all sensing pixels. The active pixel sensor device using the same active pixel sensing array can be applied to large-area sensing.

Abstract: A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: An embedded bridge rectifier is disclosed. By reconfiguring and reconnecting internal ESD protection circuits originally installed at two bonding pads of integrated circuits, the invention not only saves hardware cost of conventional external bridge rectifiers, but also reduces the space of print circuit boards.

Abstract: A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: An embedded bridge rectifier is disclosed. By reconfiguring and reconnecting internal ESD protection circuits originally installed at two bonding pads of integrated circuits, the invention not only saves hardware cost of conventional external bridge rectifiers, but also reduces the space of print circuit boards.