Patents by Inventor Po-Hsiang Chang
Po-Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145511Abstract: An image sensor includes a first sensing unit. The first sensing unit includes a pair of photodiodes formed in a substrate and spaced by a deep trench isolation structure, an outer grid over the pair of photodiodes, a color filter filled in the outer grid, and an inner grid disposed in the color filter. The color filter overlaps the pair of photodiodes. The inner grid includes a first spacer, wherein the first spacer is rotated relative to the deep trench isolation structure.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Jian-Wen LUO, Yu-Chi CHANG, Zong-Ru TU, Po-Hsiang WANG
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Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
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Publication number: 20240125995Abstract: An image sensor includes a group of sensor units and a color filter layer disposed within the group of sensor units. The image sensor further includes a dielectric structure and a plurality of polarization splitters disposed corresponding to the color filter layer. Each of the plurality of polarization splitters has a first meta element extending in a first direction from top view and a second meta element extending in a second direction from top view. The second direction is perpendicular to the first direction.Type: ApplicationFiled: October 12, 2022Publication date: April 18, 2024Inventors: Chun-Yuan WANG, Yu-Chi CHANG, Po-Hsiang WANG
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Publication number: 20240121523Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Inventors: Kai-Hao CHANG, Chun-Yuan WANG, Shin-Hong KUO, Zong-Ru TU, Po-Hsiang WANG, Chih-Ming WANG
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Publication number: 20240120639Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.Type: ApplicationFiled: August 10, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
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Publication number: 20240105619Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240096800Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Publication number: 20240086612Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
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Patent number: 11923271Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.Type: GrantFiled: July 20, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
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Patent number: 11923302Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: GrantFiled: June 30, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20240071865Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Inventors: Xinyu Bao, Lee-Chung Lu, Jyh Chwen Frank Lee, Fong-Yuan Chang, Sam Vaziri, Po-Hsiang Huang
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Publication number: 20230253226Abstract: The present invention provides a chip carrier that selectively carries a chip under test or a standard chip. The chip carrier comprises a body and a load board. The body defines a test area located on an upper surface of the body, and a first chip position is defined in the test area. The load board is detachably located in the test area, and a second chip position is defined in the load board. A standard chip is disposed within the second chip position. When the load board is located in the test area, the load board covers the first chip position and the chip under test is not disposed within the first chip position. When the chip under test is disposed within the first chip position, the load board is not located in the test area.Type: ApplicationFiled: January 9, 2023Publication date: August 10, 2023Inventors: Po-Hsiang CHANG, Sheng-Hung WANG
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Publication number: 20230057060Abstract: The present invention provides a test component extraction module having a first arm, a second arm, and a base. The second arm is connected to the first arm. The base is connected to the second arm and has a suction hole for holding a test component. Wherein a first angle is predetermined between the first arm and the second arm. When the suction hole sucks the test component attached to a surface, and the first arm gradually moves away from the surface, a second angle is between the second arm and the first arm, and the second angle is greater than the first angle.Type: ApplicationFiled: August 12, 2022Publication date: February 23, 2023Inventors: Sheng-Hung WANG, Po-Hsiang CHANG, Mei-Cheng LAI
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Publication number: 20220277976Abstract: The invention provides a chip carrier, a chip testing module and a chip handling module. The chip carrier for carrying a plurality of chips comprises a main body with an upper surface and a lower surface. The main body has a plurality of air guide holes, and two ends of each air guide hole are respectively exposed on the upper surface and the lower surface. A part of the air guide holes are defined as a first group, and the air guide holes of the first group are connected. The main body is made of conductive material.Type: ApplicationFiled: February 24, 2022Publication date: September 1, 2022Inventors: Sheng-Hung WANG, Po-Hsiang CHANG, Zhe-Min LIAO
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Publication number: 20220209493Abstract: The present invention relates to a laser diode testing system and a laser diode testing method. The method comprises the steps of moving a laser bar or a plurality of laser diodes to a first test station by means of a first transfer device; then, electrically contacting each laser diode by a first probe module in sequence; measuring electrical and optical characteristics of the laser diodes electrically contacted by the first probe module sequentially by means of a first measuring device; moving the laser bar or the plurality of laser diodes out of the first test station by means of the first transfer device, wherein a magnetic field generated by an electromagnetic generating unit of an electromagnetic slide interacts with a magnetic field of a permanent magnet of the first transfer device, so that the first transfer device is driven and moved.Type: ApplicationFiled: November 29, 2021Publication date: June 30, 2022Inventors: Sheng-Hung WANG, Po-Hsiang CHANG
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Patent number: 8734890Abstract: A method for forming a molecularly imprinted polymer biosensor includes: (a) preparing a reaction solution including an imprinting molecule, a functional monomer, an initiator, and a crosslinking agent; (b) disposing the reaction solution in a space between upper and lower substrates each of which is made of a light-transmissible material; (c) disposing on the upper substrate a photomask having a patterned hole; (d) irradiating the reaction solution through the patterned hole of the photomask and the upper substrate so that the reaction solution undergoes polymerization to form a polymer between the upper and lower substrates; (e) removing the upper substrate after the polymer is formed on the lower substrate; and (f) extracting the imprinting molecule from the polymer so that a patterned molecularly imprinted polymer film is formed on the lower substrate.Type: GrantFiled: September 24, 2010Date of Patent: May 27, 2014Assignee: National Tsing Hua UniversityInventors: Chien-Chong Hong, Po-Hsiang Chang, Chih-Chung Lin
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Publication number: 20110241260Abstract: A method for forming a molecularly imprinted polymer biosensor includes: (a) preparing a reaction solution including an imprinting molecule, a functional monomer, an initiator, and a crosslinking agent; (b) disposing the reaction solution in a space between upper and lower substrates each of which is made of a light-transmissible material; (c) disposing on the upper substrate a photomask having a patterned hole; (d) irradiating the reaction solution through the patterned hole of the photomask and the upper substrate so that the reaction solution undergoes polymerization to form a polymer between the upper and lower substrates; (e) removing the upper substrate after the polymer is formed on the lower substrate; and (f) extracting the imprinting molecule from the polymer so that a patterned molecularly imprinted polymer film is formed on the lower substrate.Type: ApplicationFiled: September 24, 2010Publication date: October 6, 2011Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Chien-Chong HONG, Po-Hsiang CHANG, Chih-Chung LIN
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Publication number: 20110066386Abstract: The invention discloses an anesthetic sensing optical microfluidic chip system. The anesthetic sensing optical microfluidic chip system includes a biochip, a light source, and a detector. The biochip includes a substrate, a micro-channel, and a molecularly imprinted biosensor. The micro-channel is bonded beyond the substrate. The molecularly imprinted biosensor is disposed in the micro-channel, and a surface of the molecularly imprinted biosensor has a plurality of imprinted sites. When a sample including a plurality of anesthetic molecules is injected into the micro-channel and flowing through the surface of the molecularly imprinted biosensor, some of the anesthetic molecules are captured by the imprinted sites. The light source emits a sensing light to the plastic biochip, and the detector receives the sensing light passing through the imprinted sites on the surface of the molecularly imprinted biosensor and generates a detecting result based on the received sensing light.Type: ApplicationFiled: September 16, 2009Publication date: March 17, 2011Inventors: Chien-Chong Hong, Po-Hsiang Chang, Chih-Chung Lin