Patents by Inventor Po-Hsiang Huang

Po-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210018009
    Abstract: A fan module comprises a frame, a wire-stopping structure, an impeller and a circuit board. The frame includes a frame wall, a base, a plurality of static blades and a connector. A wire groove formed on an outside of the frame wall to accommodate a wire. The static blades are radially connected to the base and the frame wall. The connector is formed on the outside of the frame wall and extended from one end of the wire groove to the base along one of the static blades. The connector includes a plurality of pins. The wire-stopping board is fixed to the frame wall to cover the wire groove. The impeller is disposed in the frame. The circuit board is disposed in the frame and located on the base. The circuit board includes a plurality of pin holes, and the pin holes are electrically connected to the pins.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: MING-KAI HSIEH, CHING-HSIANG HUANG, YI-FANG CHOU, PO-CHUN WANG
  • Publication number: 20210006138
    Abstract: An apparatus for assembling a permanent magnet motor rotor includes a first-end positioning assembly, a plurality of connectors, and a second-end positioning assembly. The first-end positioning assembly is utilized to fix a first-end rotor core. The second-end positioning assembly is utilized to fix a second-end rotor core. The connectors are utilized to connect and fix the first-end positioning assembly with the second-end positioning assembly. Each first longitudinal axis of each first positioning element of the first end positioning assembly is different from each second longitudinal axis of each second positioning element of the second end positioning assembly. In addition, a method for assembling a permanent magnet motor rotor is also provided.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Inventors: Ming-Hsiang CHEN, Po-Ju HUANG, Lian-Shin HUNG
  • Publication number: 20200411503
    Abstract: An integrated circuit includes a first region. The integrated circuit further includes a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first region or the second region, wherein the power structure includes a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Po-Hsiang HUANG, Lipen YUAN
  • Publication number: 20200410154
    Abstract: A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Inventors: Po-Hsiang HUANG, Sheng-Hsiung CHEN, Fong-Yuan CHANG
  • Patent number: 10878165
    Abstract: A method (of generating a layout diagram) includes: generating a cell (which represents a circuit) including first and second side boundaries which are substantially parallel and extend in a first direction, a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction (substantially perpendicular to the first direction) and represents a conductor of a first signal which is internal to the circuit, and a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit; configuring the intra-cell wiring pattern so that a first end is located substantially a minimum boundary offset interior to the first side boundary; and configuring the second wiring pattern so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang
  • Patent number: 10872918
    Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric layer. The epitaxial layer and the dielectric layer are formed in a deep trench of a semiconductor substrate. The epitaxial layer covers a lower portion of sidewall of the trench, and the dielectric layer covers an upper portion of the sidewall of the trench. In the method for fabricating the optical isolation structure, at first, shallow trenches are formed in the semiconductor substrate. Then, the dielectric layer is formed in the shallow trenches. Thereafter, deep trenches are formed passing through the dielectric layers. Then, the epitaxial layer is formed in the deep trenches.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Han Huang, Tzu-Hsiang Chen, Shih-Pei Chou, Jiech-Fun Lu
  • Publication number: 20200395281
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 10851206
    Abstract: A modified nylon 66 fiber including a first repeating unit derived from adipic acid and hexamethylenediamine, a second monomer unit derived from a diacid or a diamine having a long carbon chain, a third monomer unit derived from a diacid or a diamine having a aromatic ring, and a fourth monomer unit derived from a cyclic diacid or a cyclic diamine is provided. The second monomer unit has 6 to 36 carbon atoms. The third monomer unit has 8 to 14 carbon atoms. The fourth monomer unit has 6 to 10 carbon atoms. Based on a total weight of the modified nylon 66 fiber, a content of the first repeating unit is 78 wt % to 94.8 wt %, a content of the second monomer unit is 0.1 wt % to 1 wt %, a content of the third monomer unit is 5 wt % to 20 wt %, a content of the fourth monomer unit is 0.1 wt % to 1 wt %.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Textile Research Institute
    Inventors: Tzu-Chung Lu, Chin-Wen Chen, Wei-Hsiang Lin, Chao-Huei Liu, Po-Hsun Huang, Wei-Jen Lai
  • Patent number: 10839516
    Abstract: A simulate segmentation method of cylinder and pie cake digital models utilizes a three-dimensional model and a reference point to cope with various shapes of the nuclear reactor structures. The segmentation simulation of the nuclear reactor structure is conducted with genetic algorithm. The segmentation simulation of the nuclear reactor structure is achieved by using the genetic algorithm to perform a double selection mechanism on the cross-sectional area of the nuclear reactor structure to select the optimal configuration of the segmentation, thus minimizing the cross-sectional areas of the nuclear reactor structure. The cutter segments the nuclear reactor structure based on the optimal configuration of the segmentation, thereby achieving the purpose of minimizing the attrition rate of a cutter and segmenting the nuclear reactor structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Yu-Hsiang Hung, Chung-Hao Huang, Shiang-Fong Chen, Po-Chou Tsai
  • Publication number: 20200335340
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10796060
    Abstract: A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Li-Chun Tien, Shun-Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang
  • Patent number: 10797041
    Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan
  • Patent number: 10776557
    Abstract: A semiconductor structure includes first and second device regions. The first device region contains an entirety of a first active area of a first logic device, the second device region contains an entirety of a second active area of a second logic device, and the second device region shares a boundary with the first device region. The semiconductor structure also includes a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary, and a via contacting the first metal zero pin. A distance from the center of the via to the boundary is less than or equal to a first predetermined distance, and the via is electrically connected to one of the first logic device or the second logic device.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Sheng-Hsiung Chen, Fong-Yuan Chang
  • Patent number: 10777505
    Abstract: A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen
  • Publication number: 20200258846
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Chin-Chou LIU, Cheng-Hung YEH, Fong-Yuan CHANG, Po-Hsiang HUANG, Yi-Kan CHENG, Ka Fai CHANG
  • Patent number: 10741539
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 10707081
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Publication number: 20200184869
    Abstract: A source driver and an operating method thereof are provided. The source driver includes a high voltage circuit, a low voltage circuit and a sensing circuit. The low voltage circuit is coupled to the high voltage circuit. The high voltage circuit and low voltage circuit drive a display panel. The sensing circuit is coupled to the low voltage circuit. The sensing circuit senses the display panel during an analog-to-digital operating period. At least one of the high voltage circuit and the low voltage circuit is disabled during at least part of the analog-to-digital operating period.
    Type: Application
    Filed: June 2, 2019
    Publication date: June 11, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Po-Hsiang Fang, Jhih-Siou Cheng, Ju-Lin Huang