Abstract: Techniques for color change of Information elements (IEs) are described. In an example, a color of the IE and a color of a region of a virtual environment surrounding the IE may be compared. Based on the comparison, it may be determined whether the IE is distinguishable from the region of the virtual environment. Further, based on the determination, the color of the IE may be changed to facilitate distinguishability of the IE.

Abstract: The present disclosure provides a method and a system therefore for processing wafer. The method includes: extracting a first gas from a chamber via a first route; blocking a second route used to be pumped down to chuck a wafer placed in the chamber, wherein the second route connects the chamber and the first route; and providing a second gas via a third route to purge a junction of the first route and the second route.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Abstract: A light source assembly, a method for making same, and a display device using same are disclosed. The light source assembly includes a circuit substrate, an opaque and light-reflecting colloidal layer on the circuit substrate, micro light-emitting elements electrically connected to the circuit substrate, a base layer, a layer of convex lenses, and a layer of immediately-adjacent concave lenses. The colloidal layer defines grooves. At least two micro light-emitting elements each emitting light of a different color are arranged in each groove. The base layer is infilled into each groove and covers each micro light-emitting element. Each groove is covered by a convex lens which converges the emitted light. Each concave lens, covering one convex lens, substantially corrects optical path deviations of light of different wavelengths (that is, different colors), so reducing chromatic aberrations.

Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

Abstract: A backlight driving device and an operating method thereof are provided to drive multiple backlight zones of a backlight panel. The backlight driving device includes an interface circuit and a driving circuit. The interface circuit receives main backlight data corresponding to a first backlight zone from a former stage device. The driving circuit drives the first backlight zone according to a main current level in a display refresh period of a backlight frame period, does not drive the first backlight zone in a demotion blur period which is prior to the display refresh period, and drives the first backlight zone according to a compensation current level in a vertical blanking period which succeeds the display refresh period. The driving circuit determines the main current level according to the main backlight data, and the compensation current level is lower than the main current level.

Abstract: An intellectual quality management method is disclosed. A heatmap risk interface is created according to the required data and the parameter configuration which are calculated using a time dependent risk priority number (RPN) equation. An intellectual audit scheduling algorithm is defined via the heatmap risk interface to automatically generate at least one audit plan. An audit program corresponding to the audit plan is performed and a plurality of problem points are selected. Intellectual root cause category recommendation is performed to the questions points. intellectual corrective actions and preventive action recommendations are performed to the problem points according to the intellectual root cause category recommendation to obtain at least one optimum corrective action and at least one preventive action.

Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.

Abstract: An apparatus for assembling a permanent magnet motor rotor includes a first-end positioning assembly, a plurality of connectors, and a second-end positioning assembly. The first-end positioning assembly is utilized to fix a first-end rotor core. The second-end positioning assembly is utilized to fix a second-end rotor core. The connectors are utilized to connect and fix the first-end positioning assembly with the second-end positioning assembly. Each first longitudinal axis of each first positioning element of the first end positioning assembly is different from each second longitudinal axis of each second positioning element of the second end positioning assembly. In addition, a method for assembling a permanent magnet motor rotor is also provided.

Abstract: A micro light-emitting diode (micro LED) display and a package method thereof are described. The micro LED display includes a substrate, various micro LED chips, and an encapsulation film. The substrate includes a wire. The micro LED chips are disposed on a surface of the substrate and are electrically connected to the wire. A light-emitting surface of each of the micro LED chips is set with at least one micro structure, and each micro structure has a top end. The encapsulation film encapsulates the micro LED chips, and covers the surface of the substrate. The top ends of the micro structures are located in a light-emitting surface of the encapsulation film.

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.