Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Abstract: A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

Abstract: Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

Abstract: A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

Abstract: A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Abstract: In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over an integrated circuit device; forming a first conductive feature in the first dielectric layer; selectively depositing a polymer layer over the first conductive feature; selectively depositing an etch stop layer over the first dielectric layer adjacent the polymer layer; removing the polymer layer to form a first opening; and forming a second conductive feature in the first opening and electrically coupled to the first conductive feature.

Abstract: Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract: A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

Abstract: A structure includes a gate stack over a semiconductor region, a source/drain region on a side of the gate stack, a contact etch stop layer over a part of the source/drain region, an inter-layer dielectric over the contact etch stop layer, a silicide region over the source/drain region, a source/drain contact plug over and contacting the silicide region, and an isolation layer encircling the source/drain contact plug. In a top view of the source/drain contact plug, the source/drain contact plug is elongated, and the isolation layer includes an end portion at an end of the source/drain contact plug, and a middle portion between opposing ends of the source/drain contact plug. An end-portion thickness of the end portion is greater than a middle-portion thickness of the middle portion.

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

Abstract: A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.