Patents by Inventor Po-Hsien Yeh

Po-Hsien Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282841
    Abstract: A GaN device with N2 pre-treatment is provided in the present invention, including a GaN substrate, an AlGaN layer covering the GaN substrate, a p-GaN gate on the AlGaN layer, a TiN electrode on the p-GaN gate, a first dielectric layer on the AlGaN layer surrounding the p-GaN gate, wherein a horizontal spacing is between the first dielectric layer and the p-GaN gate, and an interface between the AlGaN layer and the GaN substrate not covered by the first dielectric layer is subject to N2 pre-treatment, and a second dielectric layer covering on and directly contacting the exposed first dielectric layer, AlGaN layer, p-GaN gate and TiN electrode.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 22, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Po-Hsien Yeh, Jih-Wen Chou, Hwi-Huang Chen, Hsin-Hong Chen, Yu-Jen Huang
  • Publication number: 20240079485
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Chih-Hung Lu, Bo-An Tsai, Zheng-Chang Mu, Po-Hsien Yeh, Robin Christine Hwang
  • Publication number: 20230299169
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, a gate structure, and a spacer is provided. The first barrier layer is disposed on the channel layer. The gate structure is disposed on the first barrier layer. The gate structure includes a first P-type gallium nitride layer, a second barrier layer, and a second P-type gallium nitride layer. The first P-type gallium nitride layer is disposed on the first barrier layer. The second barrier layer is disposed on the first P-type gallium nitride layer. The second P-type gallium nitride layer is disposed on the second barrier layer. A width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer. The spacer is disposed on a sidewall of the second P-type gallium nitride layer.
    Type: Application
    Filed: September 12, 2022
    Publication date: September 21, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Hsin-Hong Chen, Yu-Jen Huang, Robin Christine Hwang, Po-Hsien Yeh, Chih-Hung Lu