Abstract: A chromosome abnormality detecting system includes an image capturing unit and a non-transitory machine readable medium. The image capturing unit is for obtaining a target metaphase chromosomes image of a subject. The non-transitory machine readable medium storing a program which, when executed by at least one processing unit, determines whether the subject has a chromosome abnormality when executed by a processing unit. The program includes a reference database obtaining module, a reference image transforming module, a reference preliminary classifying module, a reference feature selecting module, a training module, a target image transforming module, a target preliminary classifying module, a target feature selecting module and a comparing module.

Abstract: An assisted detection system of breast tumor includes an image capturing unit and a non-transitory machine readable medium. The non-transitory machine readable medium storing a program which, when executed by at least one processing unit, determines a breast tumor type of the subject and predicts a probability of a tumor location of the subject. The program includes a reference database obtaining module, a first image preprocessing module, an autoencoder module, a classifying module, a second image preprocessing module and a comparing module.

Abstract: An assisted detection system of breast tumor includes an image capturing unit and a non-transitory machine readable medium. The non-transitory machine readable medium storing a program which, when executed by at least one processing unit, determines a breast tumor type of the subject and predicts a probability of a tumor location of the subject. The program includes a reference database obtaining module, a first image preprocessing module, an autoencoder module, a classifying module, a second image preprocessing module and a comparing module.

Abstract: The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper surface, and has a plurality of second electrical contacts. The third layout area is on the upper surface, and has a plurality of third electrical contacts. The second and the third electrical contacts that have the same electrical property are electrically connected to each other. Thus, the circuit substrate can be applied to memory chips with different size.

Abstract: The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper surface, and has a plurality of second electrical contacts. The third layout area is on the upper surface, and has a plurality of third electrical contacts. The second and the third electrical contacts that have the same electrical property are electrically connected to each other. Thus, the circuit substrate can be applied to memory chips with different size.