Patents by Inventor Po-Hsin Liu
Po-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118522Abstract: A photographing lens assembly includes, in order from an object side to an image side: a first, a second, a third, a fourth, a fifth and a sixth lens elements. The first lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, wherein the object-side surface has at least one convex critical point in an off-axis region thereof. The third lens element has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, and an image-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex critical point in an off-axis region thereof.Type: ApplicationFiled: December 7, 2023Publication date: April 11, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Po-Lun HSU, Wei-Yu CHEN, Kuan-Ting YEH, Ssu-Hsin LIU
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Patent number: 11953372Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.Type: GrantFiled: January 18, 2022Date of Patent: April 9, 2024Assignee: InnoLux CorporationInventors: Yu-Tsung Liu, Wei-Ju Liao, Wei-Lin Wan, Cheng-Hsueh Hsieh, Po-Hsin Lin, Te-Yu Lee
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Patent number: 9583589Abstract: A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.Type: GrantFiled: October 14, 2015Date of Patent: February 28, 2017Assignee: Northrop Grumman Systems CorporationInventors: Xiaobing Mei, Ling-Shine Lee, Michael D. Lange, Wayne Yoshida, Po-Hsin Liu
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Patent number: 9048184Abstract: A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.Type: GrantFiled: March 15, 2013Date of Patent: June 2, 2015Assignee: Northrop Grumman Systems CorporationInventors: Carol O. Namba, Po-Hsin Liu, Sumiko Poust, Ioulia Smorchkova, Michael Wojtowicz, Ronald Grundbacher
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Patent number: 7897446Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: March 25, 2010Date of Patent: March 1, 2011Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7800766Abstract: A method and apparatus 10 for detecting the height of non-flat and transparent substrates using one or more reflectors 30 patterned on the surface of the substrate 40 and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker 60 on the holder and using appropriate spacers 50 with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.Type: GrantFiled: September 21, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Mike Wojtowicz, Rob Coffie
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Patent number: 7800132Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: GrantFiled: October 25, 2007Date of Patent: September 21, 2010Assignee: Northrop Grumman Systems CorporationInventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Publication number: 20100184262Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: ApplicationFiled: March 25, 2010Publication date: July 22, 2010Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7750370Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: GrantFiled: December 20, 2007Date of Patent: July 6, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Ioulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Patent number: 7709860Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).Type: GrantFiled: April 29, 2009Date of Patent: May 4, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Linh Dang, Wayne Yoshida, Xiaobing Mei, Jennifer Wang, Po-Hsin Liu, Jane Lee, Weidong Liu, Michael Barsky, Richard Lai
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Publication number: 20090267115Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Patent number: 7608865Abstract: A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.Type: GrantFiled: April 28, 2008Date of Patent: October 27, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Michael Wojtowicz, Robert Coffie, Yaochung Chen
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Patent number: 7582518Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).Type: GrantFiled: November 14, 2006Date of Patent: September 1, 2009Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Linh Dang, Wayne Yoshida, Gerry Mei, Jennifer Wang, Po-Hsin Liu, Jane Lee, Weidong Liu, Mike Barsky, Rich Lai
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Publication number: 20090206369Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).Type: ApplicationFiled: April 29, 2009Publication date: August 20, 2009Applicant: NORTHROP GRUMMAN SPACE & MISSION SYSTEMS CORP.Inventors: Linh Dang, Wayne Yoshida, Xiaobing Mei, Jennifer Wang, Po-Hsin Liu, Jane Lee, Weidong Liu, Michael Barsky, Richard Lai
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Publication number: 20090159930Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Northrop Grumman Space and Mission System Corp.Inventors: loulia Smorchkova, Robert Coffie, Ben Heying, Carol Namba, Po-Hsin Liu, Boris Hikin
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Publication number: 20090108299Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Applicant: Northrop Grumman Space and Mission Systems Corp.Inventors: Ioulia Smorchkova, Carol Namba, Po-Hsin Liu, Robert Coffie, Roger Tsai
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Publication number: 20090078888Abstract: A method and apparatus 10 for detecting the height of non-flat and transparent substrates using one or more reflectors 30 patterned on the surface of the substrate 40 and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker 60 on the holder and using appropriate spacers 50 with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: Northrop Grumman Space & Mission Systems Corp.Inventors: Carol Osaka Namba, Po-Hsin Liu, Ioulia Smorchkova, Mike Wojtowicz, Rob Coffie
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Patent number: 7411226Abstract: An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.Type: GrantFiled: April 27, 2005Date of Patent: August 12, 2008Assignee: Northrop Grumman CorporationInventors: Yeong-Chang Choug, Ronald Grundbacher, Po-Hsin Liu, Denise L. Leung, Richard Lai
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Publication number: 20080111157Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Applicant: Northrop Grumman CorporationInventors: Linh Dang, Wayne Yoshida, Xiaobing Mei, Jennifer Wang, Po-Hsin Liu, Jane Lee, Weidong Liu, Michael Barsky, Richard Lai
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Publication number: 20060244009Abstract: An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Inventors: Yeong-Chang Choug, Ronald Grundbacher, Po-Hsin Liu, Denise Leung, Richard Lai