Patents by Inventor Po-Hsueh Li
Po-Hsueh Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10727061Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.Type: GrantFiled: April 6, 2018Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10269906Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.Type: GrantFiled: March 15, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Po-Hsueh Li
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Patent number: 10163718Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: GrantFiled: September 8, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
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Publication number: 20180233368Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.Type: ApplicationFiled: April 6, 2018Publication date: August 16, 2018Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20180151678Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.Type: ApplicationFiled: March 15, 2017Publication date: May 31, 2018Inventor: Po-Hsueh Li
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Patent number: 9941125Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: GrantFiled: August 31, 2015Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20180012806Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: ApplicationFiled: September 8, 2017Publication date: January 11, 2018Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
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Patent number: 9779997Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: GrantFiled: March 11, 2016Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
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Publication number: 20170194209Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: ApplicationFiled: March 11, 2016Publication date: July 6, 2017Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
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Publication number: 20170062222Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 9536980Abstract: An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.Type: GrantFiled: July 28, 2015Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Chun-Hung Lee, Hua Feng Chen, Po-Hsueh Li