Patents by Inventor Po-Hsun WANG

Po-Hsun WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098376
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: August 4, 2020
    Publication date: April 1, 2021
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20210091190
    Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.
    Type: Application
    Filed: June 11, 2020
    Publication date: March 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20210013159
    Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Patent number: 10890738
    Abstract: An optical imaging lens assembly includes five lens elements, which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The third lens element has negative refractive power. The fifth lens element has negative refractive power.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: January 12, 2021
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Kuo-Jui Wang, Chien-Hsun Wu, Wei-Yu Chen, Po-Lun Hsu
  • Publication number: 20210006150
    Abstract: A power supply device includes an inductor, a switch, a power supply, and a snubber circuit. A first terminal of the switch is coupled to a first terminal of the inductor. A first terminal of the power supply is coupled to a second terminal of the witch. A first terminal of the snubber circuit is coupled to the first terminal of the switch at a first voltage output terminal. A second terminal of the snubber circuit is electrically coupled to a second terminal of the power supply at a second voltage output terminal, in which the inductor, the switch, the power supply, and the snubber circuit are configured to cooperate to generate an output voltage at the first voltage output terminal and the second voltage output terminal.
    Type: Application
    Filed: January 21, 2020
    Publication date: January 7, 2021
    Inventors: Wei-Hsun LAI, Wei-Cheng LIN, Po-Cheng CHIU, Chien-Yu WANG
  • Publication number: 20200412244
    Abstract: A power supply circuit includes an energy storage element, a first switch, a voltage signal converter, a second switch, a third switch and a power supply. The first switch is coupled to the energy storage element at a first voltage output terminal. The voltage signal converter is coupled to, respectively, the energy storage element and the first switch at a first converter output terminal and a second converter output terminal. The second switch is coupled to the first switch. The third switch is coupled to the second switch at a second voltage output terminal. The power supply is coupled to the second switch and the third switch. The energy storage element, the first switch, the voltage signal converter, the second switch, the third switch and the power supply cooperate and generate a output voltage. A method of operating the power supply circuit is also disclosed herein.
    Type: Application
    Filed: January 16, 2020
    Publication date: December 31, 2020
    Inventors: Wei-Hsun LAI, Chien-Yu WANG, Po-Cheng CHIU, Wei-Cheng LIN
  • Publication number: 20200413526
    Abstract: An extreme ultraviolet (EUV) lithography method includes causing a first metallic droplet to move along a shroud and through an aperture of the shroud at a first velocity, and adjusting an open area of the aperture of the shroud. After adjusting the open area of the aperture of the shroud, a second metallic droplet is caused to move along the shroud and through the aperture of the shroud at a second velocity, in which the second velocity is different from the first velocity.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsun TSAI, Han-Lung CHANG, Yen-Hsun CHEN, Shao-Hua WANG, Li-Jui CHEN, Po-Chung CHENG
  • Patent number: 10818612
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A semiconductor device having a first surface and a second surface opposite to the first surface is provided. A plurality of through semiconductor vias (TSV) embedded in the semiconductor device is formed. A first seal ring is formed over the first surface of the semiconductor device. The first seal ring is adjacent to edges of the first surface and is physically in contact with the TSVs. A second seal ring is formed over the second surface of the semiconductor device. The second seal ring is adjacent to edges of the second surface and is physically in contact with the TSVs.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Publication number: 20200310737
    Abstract: In an approach for smart collaboration, a plurality of images are received. Each image of the plurality of images is from a different device of a plurality of devices. The plurality of images are combined into a single combined image. The combined image is transferred to the plurality of devices.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Der-Joung Wang, David Shao Chung Chen, Lilian Lai, Louis Huang, Wei-Te Chiang, Molly Chang, Po-Hsun Tseng, Kuo-Liang Chou
  • Patent number: 10779387
    Abstract: A method of operating an extreme ultraviolet (EUV) lithography system includes directing a metallic droplet along a shroud, wherein the shroud has a first opening adjacent a droplet generator and a second opening adjacent an excitation region; partially shielding the second opening of the shroud; and emitting a laser beam encountering the metallic droplet to generate an EUV light.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsun Tsai, Han-Lung Chang, Yen-Hsun Chen, Shao-Hua Wang, Li-Jui Chen, Po-Chung Cheng
  • Publication number: 20200243598
    Abstract: A light-emitting device, includes a substrate, including an upper surface; a first light emitting unit and a second light emitting unit, formed on the upper surface, wherein each of the first light emitting unit and the second light emitting unit includes a lower semiconductor portion and an upper semiconductor portion; and a conductive structure electrically connecting the first light emitting unit and the second light emitting unit; wherein the lower semiconductor portion of the first light emitting unit includes a first sidewall and a first upper surface; and wherein the first side wall includes a first sub-side wall and a second sub-side wall, an obtuse angle is formed between the first sub-side wall and the first upper surface and another obtuse angle is formed between the second sub-side wall and the upper surface.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 30, 2020
    Inventors: Po-Shun CHIU, Tsung-Hsun CHIANG, Liang-Sheng CHI, Jing JIANG, Jie CHEN, Tzung-Shiun YEH, Hsin-Ying WANG, Hui-Chun YEH, Chien-Fu SHEN
  • Patent number: 10679081
    Abstract: A biometric device includes a substrate, an image sensor, at least one infrared light emitting diode (IR LED), a supporting structure and an optical layer. The image sensor is disposed on the substrate. The at least one IR LED is disposed on the substrate. The supporting structure is disposed on the substrate and located between the image sensor and the at least one infrared light emitting diode. The optical layer is disposed on the supporting structure, covers the image sensor, and includes a coded pattern.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 9, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Hsin Chao, Yen-Hsiang Fang, Ming-Hsien Wu, Po-Hsun Wang
  • Publication number: 20200176574
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: May 10, 2019
    Publication date: June 4, 2020
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Publication number: 20200166848
    Abstract: A method of operating an extreme ultraviolet (EUV) lithography system includes directing a metallic droplet along a shroud, wherein the shroud has a first opening adjacent a droplet generator and a second opening adjacent an excitation region; partially shielding the second opening of the shroud; and emitting a laser beam encountering the metallic droplet to generate an EUV light.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 28, 2020
    Inventors: Ming-Hsun TSAI, Han-Lung CHANG, Yen-Hsun CHEN, Shao-Hua WANG, Li-Jui CHEN, Po-Chung CHENG
  • Publication number: 20200135641
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Application
    Filed: August 5, 2019
    Publication date: April 30, 2020
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Publication number: 20200111391
    Abstract: A spliced display including a transparent substrate, a plurality of (light-emitting diode) LED modules, at least one control element, and a signal transmission structure is provided. The transparent substrate has a display surface and a back surface opposite to each other. The LED modules are disposed on the back surface of the transparent substrate to be spliced with each other. Each of the LED modules includes a driving backplane and a plurality of micro LEDs, and the micro LEDs are disposed in an array between the driving backplane and the transparent substrate. The control element is disposed on the transparent substrate. The control element is connected to the LED modules via the signal transmission structure, and the LED modules are connected to each other via the signal transmission structure.
    Type: Application
    Filed: December 22, 2018
    Publication date: April 9, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Hsin Chao, Ming-Hsien Wu, Yen-Hsiang Fang, Po-Hsun Wang, Li-Chun Huang
  • Publication number: 20200107427
    Abstract: A droplet generator assembly includes a storage tank, a refill system, a droplet generator, and a temperature control system. The storage tank is configured to store a target material. The refill system is connected to the storage tank. The droplet generator includes a reservoir and a nozzle connected to the reservoir, in which the droplet generator is connected to the refill system, and the refill system is configured to deliver the target material to the reservoir. The temperature control system is adjacent to the refill system or the reservoir.
    Type: Application
    Filed: July 11, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Yu TU, Yu-Kuang SUN, Shao-Hua WANG, Han-Lung CHANG, Hsiao-Lun CHANG, Li-Jui CHEN, Po-Chung CHENG, Cheng-Hao LAI, Hsin-Feng CHEN, Wei-Shin CHENG, Ming-Hsun TSAI, Yen-Hsun CHEN
  • Publication number: 20200035628
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsun HUANG, Po-Han WANG, Ing-Ju LEE, Chao-Lung CHEN, Cheng-Ming WU
  • Patent number: 10541233
    Abstract: A display device including a circuit substrate, a plurality of pixels, and a light-shielding layer is provided. The pixels include a plurality of light-emitting elements. The light-emitting elements are disposed on the circuit substrate and are electrically connected to the circuit substrate. The light-emitting elements in the pixels are arranged along an arrangement direction. The light-shielding layer is disposed on the circuit substrate and has a plurality of pixel apertures. The pixels are disposed in a corresponding pixel aperture. The light-shielding layer includes a plurality of first light-shielding patterns extending in the arrangement direction and a plurality of second light-shielding patterns connected to the first light-shielding patterns. The extending direction of the second light-shielding patterns is different from the extending direction of the first light-shielding patterns.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 21, 2020
    Assignees: Industrial Technology Research Institute, Macroblock, Inc.
    Inventors: Po-Hsun Wang, Chia-Hsin Chao, Ming-Hsien Wu, Yen-Hsiang Fang, Chien-Chung Lin, Ming-Jer Kao, Feng-Pin Chang
  • Publication number: 20190371741
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A semiconductor device having a first surface and a second surface opposite to the first surface is provided. A plurality of through semiconductor vias (TSV) embedded in the semiconductor device is formed. A first seal ring is formed over the first surface of the semiconductor device. The first seal ring is adjacent to edges of the first surface and is physically in contact with the TSVs. A second seal ring is formed over the second surface of the semiconductor device. The second seal ring is adjacent to edges of the second surface and is physically in contact with the TSVs.
    Type: Application
    Filed: April 2, 2019
    Publication date: December 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin