Patents by Inventor Po-Hsun Wu

Po-Hsun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154021
    Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 9, 2024
    Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
  • Patent number: 11974506
    Abstract: A spin-orbit torque device is disclosed, which includes: a magnetic layer; and a non-magnetic layer adjacent to the magnetic layer and comprising a spin-Hall material, wherein the spin-Hall material comprises NixCu1-x alloy, and x is in a range from 0.4 to 0.8.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 30, 2024
    Assignees: NATIONAL TAIWAN UNIVERSITY, ACADEMIA SINICA
    Inventors: Po-Hsun Wu, Ssu-Yen Huang, Chia-Ling Chien, Danru Qu
  • Patent number: 11955163
    Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Publication number: 20240098406
    Abstract: A method for capturing a sound source includes: capturing a space where a microphone array is located to generate an image by a camera, wherein the microphone array is configured to receive a sound generated by the sound source and generate a sound source coordinate of the sound source relative to the microphone array; searching for a sub-image belonging to the microphone array within the images by a computing device connected to the camera; calculating a microphone coordinate of the microphone array relative to the camera by the computing device according to the sub-image; calculating a required control parameter by the computing device at least according to the sound source coordinate and the microphone coordinate; adjusting a capturing direction by the camera to capture the sound source at least according to the required control parameter.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: AVER INFORMATION INC.
    Inventors: Pang-Ti TAI, Po-Hsun WU, Yun-Long SIE
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20240038293
    Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: PO-HSUN WU, JEN-SHOU HSU
  • Patent number: 11727968
    Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 15, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11694337
    Abstract: A processing path generating method includes the following steps. An image-capturing device is moved to the first position of the region of interest to perform an image-capture on a workpiece, so as to obtain a first image. The image-capturing device is moved to a second position to perform the image-capture on the workpiece, so as to obtain a second image. A first edge characteristic and a second edge characteristic of the workpiece are obtained according to the first image and the second image. Three-dimensional edge information of the workpiece is fitted according to the first edge characteristic and the second edge characteristic. A processing path is generated according to the three-dimensional edge information.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: July 4, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Meng-Chiou Liao, Chang-Lin Wang, Chin-Ming Chen, Chien-Yi Lee, Po-Hsun Wu
  • Patent number: 11685008
    Abstract: A dodge method of machining path and a machining system is provided. By inserting a flag into an original machining path, an interference between the flag and a suction cup of a support unit is determined. A coding instruction is inserted at the interference to edit the original machining path, thereby generating an edited machining path. Therefore, when a machining equipment executes the edited machining path, the support unit may smoothly dodge a knife of the machining equipment.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: June 27, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Ting Chen, Cheng-Wei Wang, Po-Hsun Wu, Chien-Chih Liao, Jen-Ji Wang
  • Publication number: 20230116769
    Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 13, 2023
    Applicant: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11545200
    Abstract: A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: January 3, 2023
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11506489
    Abstract: A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 22, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Sheng Tseng, Po-Hsun Wu, Tsung-Yu Yang, Chien-Yi Lee
  • Publication number: 20220303452
    Abstract: A method of image processing includes: capturing a first video streaming from a physical environment using an image capturing device; conducting image processing on the first video streaming to provide a second video streaming to a virtual camera module; capturing a frame of a display area of a display device when the virtual camera is opened by an application; acquiring a position of the second video streaming in a frame of the display area, and generating a user interface according to the position of the second video streaming if the frame of the display area comprises the second video streaming; and receiving an operation instruction through the user interface, and operating the image capturing device according to the operation instruction.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 22, 2022
    Inventors: Po-Hsun WU, Yun-Long SIE
  • Publication number: 20220158084
    Abstract: A spin-orbit torque device is disclosed, which includes: a magnetic layer; and a non-magnetic layer adjacent to the magnetic layer and comprising a spin-Hall material, wherein the spin-Hall material comprises NixCu1-x alloy, and x is in a range from 0.4 to 0.8.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Inventors: Po-Hsun WU, Ssu-Yen HUANG, Chia-Ling CHIEN, Danru QU
  • Patent number: 11100963
    Abstract: A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 24, 2021
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11010528
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 18, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
  • Patent number: 10916293
    Abstract: A target row refresh method includes: providing first table having M entries each capable of storing information of target row address; providing second table having K entries respectively capable of storing information of different/identical candidate row addresses; determining whether an input address in an input address register matches address information recorded in the first table; when not match, determining whether to update information of a target row latch by using the input address in the input address register according to a sample policy so as to determine whether to compare the input address with address information recorded in the second table to determine a target row address; and performing a target row refresh operation to refresh a memory device's row(s) adjacent to a target row corresponding to the target row address.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 9, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Ya-Chun Lai, Po-Hsun Wu, Jen-Shou Hsu
  • Publication number: 20200326185
    Abstract: A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.
    Type: Application
    Filed: July 31, 2019
    Publication date: October 15, 2020
    Inventors: Yu-Sheng Tseng, Po-Hsun Wu, Tsung-Yu Yang, Chien-Yi Lee
  • Publication number: 20200150859
    Abstract: A method of operating a widget on an electronic device comprises the following steps. Step 1 is to display a widget on a display surface of the electronic device. Step 2 is to transmit the identification information corresponding to the widget to a desktop management program by the widget. Step 3 is to obtain a size information and a location information corresponding to the widget according to the identification information by the desktop management program. Step 4 is to generate an editable window based on the size information and the location information on the display surface corresponding to the widget.
    Type: Application
    Filed: October 1, 2019
    Publication date: May 14, 2020
    Inventor: Po-Hsun Wu
  • Publication number: 20200142569
    Abstract: A method of freezing a screen includes the following operations: stop updating content of a bottom layer of a plurality of layers of an image shown on a screen in response to a first command; and displaying a content of a predetermined layer of the plurality of layers on the image.
    Type: Application
    Filed: August 13, 2019
    Publication date: May 7, 2020
    Inventor: Po-Hsun WU