Patents by Inventor Po-Hua Wu

Po-Hua Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240391312
    Abstract: A fuel tank cap includes a seal cap body and a detaching-proof unit. The cap body has a handheld wall and a surrounding wall that extends from the handheld wall and that is formed with an engaging groove. The detaching-proof unit includes a ring sleeve member and a connection member. The ring sleeve member has an outer ring wall that surrounds the surrounding wall, and a resilient wall that extends the outer ring wall and that is engaged resiliently with the engaging groove. The connection member is connected to the ring sleeve member to be connected to a cap installation portion of a vehicle body.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 28, 2024
    Applicant: COPLUS INC.
    Inventor: Po-Hua WU
  • Publication number: 20240371803
    Abstract: A method is provided for forming a redistribution layer (RDL) structure. An RDL feature is formed over a die, and the RDL feature is electrically connected to a contact of the die. A passivation layer is formed over the RDL feature. A patterned etch mask layer is formed over the passivation layer, and has an opening over a portion of the RDL feature. The passivation layer is patterned using the patterned etch mask layer disposed thereon. The patterned etch mask layer is removed after the passivation layer is patterned using the patterned etch mask layer disposed thereon. The passivation layer is etched to form a passivation opening in the passivation layer, and the portion of the RDL feature is exposed through the passivation opening.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Wen SU, Shi-Hua TZENG, Tsung-Huan WU, Po-Chi WU
  • Publication number: 20240363467
    Abstract: In order to reduce the incidence of stress concentration areas in an etched opening, a thinner polyimide layer is deposited to minimize gap formation therein, and a descum process is then performed to increase the angle of the presented layer surface. Reduction of the stress in this manner reduces the incidence of cracking of the later formed metal contact, which improves the overall pass rates of semiconductor devices so manufactured.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Jui-Wen SU, Shi-Hua TZENG, Chih-Hung LU, Po-Chi WU
  • Publication number: 20240347626
    Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: TSUNG-HUA YANG, CHENG-BO SHU, CHIA-TA HSIEH, PING-CHENG LI, PO-WEI LIU, SHIH-JUNG TU, TSUNG-YU YANG, YUN-CHI WU, YU-WEN TSENG
  • Patent number: 12120843
    Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 15, 2024
    Assignee: Delta Electronics, Inc.
    Inventors: Chia-Feng Wu, Chien-Sheng Lin, Ming-Lung Liu, Hsin-Ming Hsu, Yun-Hua Chao, Po-Tsun Chen, Yueh-Lung Huang, Jung-Yuan Chen, Yu-Cheng Lin
  • Publication number: 20240332086
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20240332087
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20240332126
    Abstract: Thermal dissipation and grounding of integrated circuit (IC) devices with backside power delivery networks are discussed. An IC device layer between frontside and backside interconnect sections, composed mostly of an insulating material, is coupled to a crystalline heat spreader or a metal thermal ground layer by an array of thermal pillars extending through the insulating material. The crystalline heat spreader layer may include one or more thermal sensors, such as thermal sensing diodes, also coupled to the IC device layer by one or more thermal pillars. The IC device layer and crystalline layers are coupled by a hybrid bond, which forms the thermal pillars through a continuous section of the insulating material.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Andy Wei, Po-Yao Ke, Kai-Chiang Wu, Han-wen Lin, Klaus Max Schruefer, Dean Huang, Hsin-Hua Wang
  • Patent number: D1043472
    Type: Grant
    Filed: March 5, 2024
    Date of Patent: September 24, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1044612
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: October 1, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1044615
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 1, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1045203
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: October 1, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1045204
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: October 1, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1046233
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 8, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1049443
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: October 29, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1049955
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: November 5, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1050967
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 12, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1050970
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: November 12, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1051448
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: November 12, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu
  • Patent number: D1051787
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 19, 2024
    Assignee: COPLUS INC.
    Inventor: Po-Hua Wu