Abstract: A semiconductor device includes a memory array. The memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. The first memory cell is configured to generate a first current signal at a first node, in response to the first data. The second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. When the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. The second data value is a negative value of the first data value.

Abstract: A semiconductor device including at least one sense amplifier, a first memory array that includes first segments of first memory cells situated on a first side of the at least one sense amplifier, a second memory array that includes second segments of second memory cells situated on a second side of the at least one sense amplifier, first reference cells connected to first reference word lines in the first memory array for sensing data from the second memory cells and second reference cells connected to second reference word lines in the second memory array for sensing data from the first memory cells. The first reference cells connected to one of the first reference word lines for sensing data from one of the second segments and the first reference cells connected to another one of the first reference word lines for sensing data from another one of the second segments.

Abstract: A device for assessing early dementia by testing gripping strength comprises a main member, a sensing member, and a control system. The main member has a display portion and a gripping portion. The sensing member is connected to the gripping portion to be pressed by a subject to generate a sensing signal. The control system is provided in the main member and having a control unit, a timer, a grip sensing module, and a determining module. The timer records a pressing time of the subject. The grip sensing module receives the sensing signal from the sensing members and generates a gripping strength signal according to the sensing signals. The determining module receives the pressing time and the gripping strength signal, and generates an assessing result by comparing the gripping strength signal with a gripping strength threshold and comparing the pressing time with a time threshold.

Abstract: Provided is a method of accurate and sensitive characterization and prognosis of prostate cancer in a subject. The method includes obtaining a biological sample from the subject and determining the level of identified biomarkers.

Abstract: A method for depositing an electrically conductive layer on a surface of a three-dimensional (3D) electronic assembly comprising at least one electronic device embedded in a solid polymer material. The method comprises the steps of (i) providing a 3D electronic assembly, (ii) forming at least one flow barrier in the surface of the solid polymer material of the 3D electronic assembly, and (iii) depositing an electrically conductive layer on at least a portion of the surface of the solid polymer material, such that the electrically conductive layer is at least partially delimited by the flow barrier. The present invention also relates to an associated 3D electronic assembly.

Abstract: A semiconductor device includes a substrate, a stiffener ring over the substrate, and an adhesive ring between the substrate and the stiffener ring. The adhesive ring includes a first part, a second part and a third part disposed between the first part and the second part. The first part and the second part have a first thickness, and the third part has a second thickness greater than the first thickness. The third part of the adhesive ring is covered by the stiffener ring.

Abstract: A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

Abstract: A semiconductor device includes a memory array. The memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. The first memory cell is configured to generate a first current signal at a first node, in response to the first data. The second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. When the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. The second data value is a negative value of the first data value.

Abstract: A semiconductor device includes a substrate, an electronic component, a stiffener ring and an adhesive ring. The substrate has a first surface and a second surface opposite to the first surface. The electronic component is over the first surface of the substrate. The stiffener ring is over the first surface of the substrate. The stiffener ring includes a plurality of side parts and a plurality of corner parts coupled to the side parts. Heights of the corner parts are less than heights of the side parts. The adhesive ring is interposed between the first surface of the substrate and the stiffener ring. The adhesive ring includes a plurality of side portions and a plurality of corner portions coupled to the side portions. Thicknesses of the side portions are less than thicknesses of the corner portions.

Abstract: A shaping apparatus for shaping a workpiece includes a controlling module and a pressing module, a moving module, a sensing module and a shaping calculation module that are connected to the controlling module. The pressing module includes two pressing elements respectively applying load to a top/bottom surface of the workpiece. The moving module includes a moving platform moving the workpiece horizontally between a sensing zone and a processing zone. The sensing module performs a capturing process on the workpiece in the sensing zone to obtain a surface information. The shaping calculation module compares the surface information with an ideal shape data to calculate and get a shaping information. The moving platform moves the workpiece to the sensing zone. The sensing module performs a capturing process on the workpiece. The moving platform moves the workpiece to the processing zone. The pressing module performs a shaping treatment on the workpiece.

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A distributed key generation system and a key generation method are provided. The distributed key generation system includes a plurality of electronic devices and a server device. Each electronic device sends a data fragment. The server device synthesizes the key according to the data fragments. In this way, the key is not generated in advance, which can reduce the risk of key leakage.

Abstract: An electronic door lock and a method for automatically judging a locking/unlocking direction of the electronic door lock are provided. The electronic door lock includes a latch assembly, a lock body, a transmission rod, a locking detection module, a motor module and a motion detection circuit board. The transmission rod is connected with the latch assembly for controlling the latch assembly. The motion detection circuit board is electrically connected with the motor module and the locking detection module. The motion detection circuit board controls the motor module to drive the transmission rod. Consequently, a latch bolt of the latch assembly is protruded out in a first direction or a second direction. By detecting the status of the transmission rod, the locking detection module judges whether the latch bolt is protruded to a locking position.

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Abstract: A forming method of a processing curve in a stamping process is provided. The method includes the following steps. A plurality of processing curves are established, and an optimization target is set for the processing curves according to material characteristics of a workpiece, process requirements and a finished product CAD file. At least two of the processing curves are selected and superimposed to form a basic forming curve, wherein each subsection of the basic forming curve corresponds to a selected processing curve. Whether the selected processing curve in each subsection of the basic forming curve matches the optimization target is determined.

Abstract: The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results.

Abstract: A removal apparatus of a threaded post contains: a drive rod, a connection element, an actuation element, and a slidable sleeve. The connection element includes a locking groove and a notch. The actuation element includes a fitting fringe corresponding to the connection element, a cylindrical neck having a diameter less than a diameter of the fitting fringe, and an engagement disc having a diameter more than the diameter of the cylindrical neck. The diameter of fitting fringe is equal to a diameter of the connection element. The slidable sleeve includes a coupling space having a diameter equal to the diameter of the fitting fringe and the diameter of the connection element. The slidable sleeve is slid so that the coupling space abuts against the fitting fringe and the connection element, and the engagement disc is engaged in the locking groove.