Patents by Inventor Po-Hung Lee

Po-Hung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984485
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240113010
    Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 4, 2024
    Inventors: Po-Hsien Huang, Yu-Huei Lee, Hsin-Hung Lin, Chun-Yuan Shih, Lien-Chieh Yu
  • Patent number: 11929561
    Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: I-Shu Lee, Chih-Hung Cho, Hau Yuen Tan, Chien-Yi Wu, Po-Sheng Chen, Chao-Hsu Wu, Yi Chen, Hung-Ming Yu, Chih-Chien Hsieh
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20240079267
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
  • Patent number: 11923034
    Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Publication number: 20180212507
    Abstract: A multi-function power converting apparatus including an inverter circuit and a controller is provided. The inverter circuit drives a load. The controller generates a control signal according to a sampled DC voltage, a sampled AC voltage, a load current, and an output current. The controller causes the inverter circuit to enter an uninterruptible power supply mode or a grid-connected power supply mode through the control signal. Specifically, when the inverter circuit enters the grid-connected power supply mode, the multi-function power converting apparatus operates in one of a mixed real-virtual power output mode, a rectification charging mode, an active filtering mode, and an active power balancing mode.
    Type: Application
    Filed: November 28, 2017
    Publication date: July 26, 2018
    Applicant: National Tsing Hua University
    Inventors: Tsai-Fu Wu, Po-Hung Lee, Cheng-Kuang Hsieh, Jeng-Jang Hsu