Patents by Inventor Po-Jau Tsao

Po-Jau Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Four transistor static-random-access-memory cell
    Patent number: 6646310
    Abstract: A four-transistor SRAM cell, which could be viewed as at least including two word line terminals, comprises the following elements: a first word line terminal, a second word line terminal, a first bit line terminal, a second bit line terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is coupled to the first word line terminal and the source of the first transistor is coupled to the first bit line terminal, the gate of the second transistor is coupled to the second word line terminal and the source of the second transistor is coupled to the second bit line terminal, the source of the third transistor is coupled to the drain of the first transistor and the gate of the third transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor is coupled to the drain of the first transistor.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: November 11, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yuan Hsiao, Po-Jau Tsao
  • Four transistors static-random-access-memory cell
    Publication number: 20020047149
    Abstract: A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor.
    Type: Application
    Filed: July 26, 2001
    Publication date: April 25, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Yuan Hsiao, Po-Jau Tsao
  • Four transistors static-random-access-memory cell
    Patent number: 6366493
    Abstract: A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: April 2, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yuan Hsiao, Po-Jau Tsao