Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A multi-board mid-plane includes a disk backplane board (DBB) having a front side and a rear side. Venting holes are provided within the DBB extending between the front side of the DBB and the rear side of the DBB. The multi-board mid-plane also includes a controller backplane board (CBB) having a front side and a rear side. The front side of the CBB includes venting holes provided within the CBB extending between the front side of the CBB and the rear side of the CBB. A top fabric plane board (TFPB) and a bottom fabric plane board (BFPB) are provided for connecting the DBB with the CBB. A combination of the DBB and the CBB has a venting ratio that is equal to a lower of the venting ratio of the DBB and the venting ratio of the CBB.

Abstract: A multi-board mid-plane includes a disk backplane board (DBB) having a front side and a rear side. Venting holes are provided within the DBB extending between the front side of the DBB and the rear side of the DBB. The multi-board mid-plane also includes a controller backplane board (CBB) having a front side and a rear side. The front side of the CBB includes venting holes provided within the CBB extending between the front side of the CBB and the rear side of the CBB. A top fabric plane board (TFPB) and a bottom fabric plane board (BFPB) are provided for connecting the DBB with the CBB. A combination of the DBB and the CBB has a venting ratio that is equal to a lower of the venting ratio of the DBB and the venting ratio of the CBB.

Abstract: A package structure for an electronic component is disclosed. The package structure includes a box body and a first cutting line. The first cutting line is formed at the box body and defines a first plate. The first plate can be detached from the box body along the first cutting line and forms a connecting hole for the electronic component. The package structure is used as an environmental friendly computer assembly casing and solves the problem of buying an additional computer assembly casing.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.

Abstract: An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.