Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.

Abstract: A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.

Abstract: A synchronization signal extraction device includes a signal reception terminal for receiving a composite video signal, a threshold voltage adjuster coupled to the signal reception terminal for adjusting a threshold voltage to a ratio of a first characteristic level and a second characteristic level of the composite video signal according to the first characteristic level and the second characteristic level, a slicer coupled to the signal reception terminal and the threshold voltage adjuster for slicing the composite video signal to extract a synchronization signal in the composite video signal, and a signal output terminal coupled to the slicer for outputting the extracted synchronization signal.

Abstract: A low voltage differential signaling (LVDS) transmitter receives a data signal, a data invert signal and a plurality of logic signals. The LVDS transmitter includes a first-stage differential signaling transmitting circuit and a second-stage differential signaling transmitting circuit. The first-stage differential signaling transmitting circuit receives the data signal and the data invert signal and has a first output terminal and a second output terminal. The second-stage differential signaling transmitting circuit is controlled by the logic signals, and has a third output terminal and a fourth output terminal respectively connected to the first output terminal and the second output terminal, so as to generate a needed pre-emphasis signal. When no pre-emphasis signal needs to be generated, the second-stage differential signaling transmitting circuit is controlled to be in disabled state.

Abstract: A low voltage differential signaling (LVDS) transmitter receives a data signal, a data invert signal and a plurality of logic signals. The LVDS transmitter includes a first-stage differential signaling transmitting circuit and a second-stage differential signaling transmitting circuit. The first-stage differential signaling transmitting circuit receives the data signal and the data invert signal and has a first output terminal and a second output terminal. The second-stage differential signaling transmitting circuit is controlled by the logic signals, and has a third output terminal and a fourth output terminal respectively connected to the first output terminal and the second output terminal, so as to generate a needed pre-emphasis signal. When no pre-emphasis signal needs to be generated, the second-stage differential signaling transmitting circuit is controlled to be in disabled state.

Abstract: A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.

Abstract: A driving circuit includes a first switchable current module for providing a first current, a second switchable current module for providing a second current, a first switchable current source having an input end coupled to a first output end of the second switchable current module, a second switchable current source having an input end coupled to a second output end of the second switchable current module, a third switchable current source having an input coupled to a first output end of the first switchable current module, a fourth switchable current source having an input end coupled to a second output end of the first switchable current module, and a termination impedance circuit. The termination impedance circuit has a first end coupled to the first switchable current source and the third switchable current source, and a second end coupled to the second switchable current source and the fourth switchable current source.