Patents by Inventor Po-Jui Liao
Po-Jui Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160097917Abstract: A five-piece optical lens for capturing image and a five-piece optical module for capturing image, along the optical axis in order from an object side to an image side, include a first lens with positive refractive power having a convex object-side surface; a second lens with refractive power; a third lens with refractive power; a fourth lens with refractive power; and a fifth lens with negative refractive power; and at least one of the image-side surface and object-side surface of each of the five lens elements are aspheric. The optical lens can increase aperture value and improve the imagining quality for use in compact cameras.Type: ApplicationFiled: January 26, 2015Publication date: April 7, 2016Applicant: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.Inventors: KUO-YU LIAO, HUNG-KUO YU, PO-JUI LIAO, HUNG-WEN LEE, NAI-YUAN TANG, YEONG-MING CHANG
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Patent number: 9240459Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.Type: GrantFiled: February 22, 2013Date of Patent: January 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hung Huang, Jie-Ning Yang, Yao-Chang Wang, Chi-Sheng Tseng, Po-Jui Liao, Shih-Chang Chang
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Patent number: 9147678Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.Type: GrantFiled: January 4, 2012Date of Patent: September 29, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Shu-Hsuan Chih, Po-Kuang Hsieh, Chia-Chen Sun, Po-Cheng Huang, Shih-Chieh Hsu, Chi-Horn Pai, Yao-Chang Wang, Jie-Ning Yang, Chi-Sheng Tseng, Po-Jui Liao, Kuang-Hung Huang, Shih-Chang Chang
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Patent number: 9001437Abstract: An imaging lens assembly includes first, second and third optical lenses that are arranged sequentially from an object side to an image side along an optical axis, and a constant-aperture diaphragm disposed between the second optical lens and the object side. Each of the first and second optical lenses has a positive refractive power near the optical axis. The third optical lens has a negative refractive power near the optical axis and has an object-side surface and an image-side surface, at least one of which has at least an inflection point. The imaging lens assembly satisfies: 0.55<f/Dg<0.85, in which, f is a focal length of the imaging lens assembly, and Dg is a length of a diagonal line of a maximum viewing angle in an imaging plane.Type: GrantFiled: December 27, 2013Date of Patent: April 7, 2015Assignee: Ability Opto-Electronics Technology Co., Ltd.Inventors: Kuo-Yu Liao, Chen-Hung Tsai, Po-Jui Liao, Chao-Hsiang Yang
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Patent number: 8999830Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: December 19, 2013Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8952451Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: GrantFiled: December 20, 2013Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140339652Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Publication number: 20140334018Abstract: An imaging lens assembly includes first, second and third optical lenses that are arranged sequentially from an object side to an image side along an optical axis, and a constant-aperture diaphragm disposed between the second optical lens and the object side. Each of the first and second optical lenses has a positive refractive power near the optical axis. The third optical lens has a negative refractive power near the optical axis and has an object-side surface and an image-side surface, at least one of which has at least an inflection point. The imaging lens assembly satisfies: 0.55<f/Dg<0.85, in which, f is a focal length of the imaging lens assembly, and Dg is a length of a diagonal line of a maximum viewing angle in an imaging plane.Type: ApplicationFiled: December 27, 2013Publication date: November 13, 2014Applicant: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Kuo-Yu Liao, Chen-Hung Tsai, Po-Jui Liao, Chao-Hsiang Yang
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Publication number: 20140242770Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hung Huang, Jie-Ning Yang, Yao-Chang Wang, Chi-Sheng Tseng, Po-Jui Liao, Shih-Chang Chang
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Patent number: 8802524Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.Type: GrantFiled: March 22, 2011Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
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Patent number: 8753968Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.Type: GrantFiled: October 24, 2011Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Kuang-Hung Huang, Po-Jui Liao, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang
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Publication number: 20140127892Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: ApplicationFiled: December 19, 2013Publication date: May 8, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8704294Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: June 13, 2011Date of Patent: April 22, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140103443Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8692334Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: July 24, 2013Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Publication number: 20130307084Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8574990Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.Type: GrantFiled: February 24, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Shui-Yen Lu, Pei-Yu Chou, Shin-Chi Chen, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chan-Lon Yang, Teng-Chun Tsai, Chun-Hsien Lin
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Publication number: 20130241002Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Patent number: 8524556Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.Type: GrantFiled: March 14, 2012Date of Patent: September 3, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Mao Chiou, Ti-Bin Chen, Tsung-Min Kuo, Shyan-Liang Chou, Yao-Chang Wang, Chi-Sheng Tseng, Jie-Ning Yang, Po-Jui Liao
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Publication number: 20130168816Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Shu-Hsuan Chih, Po-Kuang Hsieh, Chia-Chen Sun, Po-Cheng Huang, Shih-Chieh Hsu, Chi-Horn Pai, Yao-Chang Wang, Jie-Ning Yang, Chi-Sheng Tseng, Po-Jui Liao, Kuang-Hung Huang, Shih-Chang Chang